DUAL BUS ARCHITECTURE Search Results

Pm25LD

Abstract: SI1001
Contextual Info: FEATURES 256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface Output SPI Bus Interface Pm25LD025C Memory With 100 MHz DualOutput SPI Bus Interface Memory With 100 MHz Dual-Output SPI Bus Interface • Low Power Consumption

NMA2415SC

Abstract: NKE0505DC NMS0505C ndy2405c NTE0505MC nma2412sc bwr-15/275-d5a-c NDY2409C BMP-15/1.3-D48-C DATEL BWR-12/335-D5A-C
Contextual Info: DC/DC Converters Isolated Point-of-Load Bus Converters Processor Support Memory Support www.murata-ps.com Overview PoL Converters Bus Converters Isolated Single Isolated Dual/Bipolar Isolated Dual/Asymmetric Isolated Triple Processor Power Memory Support 2

60x-bus

Abstract: AN2335 PowerPC 60X Bus Interface controller MPC107 MPC8260 bus arbiter
Contextual Info: Freescale Semiconductor, Inc. Application Note AN2335/D Rev. 0, 10/2002 Freescale Semiconductor, Inc. MPC8260 Dual-Bus Architecture and Performance Considerations Eric Bost, NCSG Field Applications, France Paul Wilson, NCSD Applications, Scotland This document describes the dual-bus architecture of the MPC8260 PowerQUICC II and

16C954

Abstract: OX16C952 16C952 Oxford Semiconductor 16c550 16C550 16C950 IEEE1284 OX16C950 OXMPCI952-LQAG
Contextual Info: OXmPCI952 DATA SHEET Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface. FEATURES • • • • • • • • • • • • Dual 16C950 High performance UART channels 8-bit Pass-through Local Bus PCI Bridge

Contextual Info: 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

IES5502TR

Abstract: IES5502 IES5502T BC857BS IES5502D DTC124E IES5501 UM10204 IES5502TR hendon
Contextual Info: IES5502 Fast Dual Bi-Directional Bus Buffer with Hot Insertion Logic 1 3 FEATURES • Dual, bi-directional unity gain isolating buffer The IES5502 is a monolithic bipolar integrated circuit for bus buffering in applications including I2C, SMBus, PMbus, and other systems based on similar principles.It

Contextual Info: In te l 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device -Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

DAC89EX

Abstract: dac86ex RBS 2111 ad42497 DAC0803 RBS 2101 ad429 AD427 AD4249 AD6422
Contextual Info: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter

ADSP21XX block diagram

Abstract: addressing modes in adsp-21xx taa 723 to 99 ADSP-21xx block diagram hip 051 57 marking Dt0 ADSP-2100 HA20 ADSP-2103 ADSP-2105
Contextual Info: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter

ADSP-2115

Contextual Info: ANALOG DEVICES AD SP-2100 Family DSP Microcomputers ADSP-21 xx SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

D2322

Abstract: ADSP-2100 ADSP2104 ADSP-2104 ADSP-2104L ADSP-2109 eprom 2764 "vector instructions" saturation
Contextual Info: a Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

Contextual Info: ANALOG ► DEVICES ADSP-2100 Family DSP Microcomputers ADSP-21XX FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

82389

Abstract: Multibus ii protocol BUS22 B1 intel 82389 Multibus II Bus Interface Controller IEEE-1296 Multibus arbitration protocol multibus II architecture specification multibus multibus ARCHITECTURE
Contextual Info: 82389 Message Passing Coprocessor A Multibus II Bus Interface Controller Datasheet Product Features • ■ Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

IEEE-1296

Abstract: BA017 BA011 271091 M82389 D1301S Multibus ii protocol 176526 BA022 BAD29
Contextual Info: in te i M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER M ilita ry Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

OXuPCI952-LQAG

Abstract: OXuPCI952 Dual 16C950 UART OXUPCI952 oxupci954 infrared transmitter receiver 555 16C550 16C950 16C954 IEEE1284 OX16C950
Contextual Info: OXuPCI952 DATA SHEET Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port, 3.3 V and 5.0 V Universal Voltage PCI Interface. FEATURES • • • • • • • • • • • • Dual 16C950 High performance UART channels 8-bit Pass-through Local Bus PCI Bridge

stpa

Abstract: MH89760B MT8920B MT8920BC MT8920BE MT8920BP MT8920BS MT8976 MT8979 tx-1c
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 6 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

sp2111

Abstract: SP-2111 plc analog em 231 ADSP-2115-BP-55 marking YJ AM marking code BM 68A
Contextual Info: ANALOG DEVICES □ ADSP-2100 Family DSP Microcomputers ADSP-21 xx FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

74AC11873

Contextual Info: 74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 – JANUARY 1990 – REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes

74AC11873

Contextual Info: 74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 – JANUARY 1990 – REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes

74AC11873

Contextual Info: 74AC11873 DUAL 4ĆBIT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS ăą SCAS095 − JANUARY 1990 − REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes

SP-2111

Abstract: eprom 2764
Contextual Info: ANALOG ► DEVICES ADSP-2100 Family DSP Microcomputers FUNCTIONAL BLOCK DIAGRAM SUM M ARY 16-Bit Fixed-Point DSP M icroprocessors w ith On-Chip Memory Enhanced Harvard Architecture for Three-Bus Perform ance: Instruction Bus & Dual Data Buses Independent Com putation Units: A LU , Multiplier/

2104 RAM

Contextual Info: ANALOG DEVICES Low Cost DSP Microcomputers A36F-2104/ASF-2109 SUM M AR Y 16-Bit Fixed-Point DSP Microprocessors w ith On-Chip M em ory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Com putation Units: ALU, M ultiplier/

82430LX

Contextual Info: in te * 82433LX/82433NX LOCAL BUS ACCELERATOR LBX Supports th e Full 64-bit Pentium- Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Drives 3.3V Signal Levels on the CPU

74ACT11873

Contextual Info: 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3–STATE OUTPUTS SCAS096 – FEBRUARY 1990 – REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture to Optimize