Untitled
Abstract: No abstract text available
Text: Digital Circuits RAY I and II Series T T L Cont. Type1 Number Description RF9601 Retriggerable monostable multivibrator RF9602 (-5 5°C to +125°C) Retriggerable monostable multivibrator (0°C to +75°C) Dual 4 input NAND gate Dual 4 input NAND gate Dual 4 input N AN D gate
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RF9601
15/gate
RF9602
30/gate
RG100
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74AUP2G00DC
Abstract: 74AUP2G00 74AUP2G00GD 74AUP2G00GT JESD22-A114E JESD78
Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 04 — 5 June 2008 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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74AUP2G00
74AUP2G00
74AUP2G00DC
74AUP2G00GD
74AUP2G00GT
JESD22-A114E
JESD78
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74aup2g00dc
Abstract: No abstract text available
Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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74AUP2G00
74AUP2G00
74aup2g00dc
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74AUP2G00DC
Abstract: 74AUP2G00 74AUP2G00GT JESD78
Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 5 — 21 October 2010 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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74AUP2G00
74AUP2G00
74AUP2G00DC
74AUP2G00GT
JESD78
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Untitled
Abstract: No abstract text available
Text: 74AUP2G132 Low-power dual 2-input NAND Schmitt trigger Rev. 5 — 1 December 2011 Product data sheet 1. General description The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals
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74AUP2G132
74AUP2G132
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Untitled
Abstract: No abstract text available
Text: 74HC2G00; 74HCT2G00 Dual 2-input NAND gate Rev. 5 — 26 September 2013 Product data sheet 1. General description The 74HC2G00; 74HCT2G00 is a dual 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess
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74HC2G00;
74HCT2G00
74HCT2G00
74HC2G00:
74HCT2G00:
JESD22-A114E
JESD22-A115-A
HCT2G00
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sot73
Abstract: HEF4012BPN HEF4012BP HEF4012BT HEF4012BD HEF4012B HEF4012BTD
Text: HEF4012B gates J DUAL 4-INPUT NAND GATE The HEF4012B provides the positive dual 4-input NAND function. The outputs are fu lly buffered for highest noise immunity and pattern insensitivity o f output impedance. J^Ui^UWUi^lJgLJTL V qd O j D 5 9 Oì Is I7 ¡6
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HEF4012B
HEF4012BP
14-lead
OT27-1)
HEF4012BD
HEF4012BT
sot73
HEF4012BPN
HEF4012BTD
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hef4012bp
Abstract: No abstract text available
Text: HEF4012B gates DUAL 4-INPUT NAND GATE The HEF4012B provides the positive dual 4-input NAND function. The outputs are fu lly buffered fo r highest noise im m unity and pattern insensitivity o f ou tp u t impedance. fcl_l^J^UiT_r5U9T_m Vqd D o, o2 la I7 *6 I 5 n.c.
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HEF4012B
HEF4012B
HEF4012BP
14-lead
OT27-1!
HEF4012BD
HEF4012BT
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Untitled
Abstract: No abstract text available
Text: 74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 7 — 5 June 2012 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to
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74AUP2G38
74AUP2G38
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JEDEC MO-187
Abstract: 74HC2G00 cmos Nand gate data sheet 74HC 74HC2G00DC 74HC2G00DP 74HCT2G00 74HCT2G00DC 74HCT2G00DP
Text: 74HC2G00; 74HCT2G00 Dual 2-input NAND gate Rev. 03 — 5 April 2006 Product data sheet 1. General description The 74HC2G00; 74HCT2G00 is a high-speed Si-gate CMOS device. The 74HC2G00; 74HCT2G00 provides the 2-input NAND function. 2. Features • ■ ■ ■
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74HC2G00;
74HCT2G00
74HCT2G00
EIA/JESD22-A114-C
EIA/JESD22-A115-A
HCT2G00
JEDEC MO-187
74HC2G00
cmos Nand gate data sheet
74HC
74HC2G00DC
74HC2G00DP
74HCT2G00DC
74HCT2G00DP
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Untitled
Abstract: No abstract text available
Text: 74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 7 — 5 June 2012 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to
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74AUP2G38
74AUP2G38
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74AUP2G38
Abstract: 74AUP2G38DC 74AUP2G38GT
Text: 74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 5 — 23 September 2010 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to
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74AUP2G38
74AUP2G38
74AUP2G38DC
74AUP2G38GT
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4 inputs OR gate truth table
Abstract: 74LS20 TTL 74ls20 truth table NAND gate 74 74Ls20 truth table 751A-02 4 inputs OR gate datasheet truth table NOT gate 74 74LS20 2 input SN74LSXXN
Text: SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN
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SN54/74LS20
51A-02
SN54LSXXJ
SN74LSXXN
SN74LSXXD
4 inputs OR gate truth table
74LS20
TTL 74ls20
truth table NAND gate 74
74Ls20 truth table
751A-02
4 inputs OR gate datasheet
truth table NOT gate 74
74LS20 2 input
SN74LSXXN
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NC7WZ00
Abstract: NL27WZ00 NL27WZ00US
Text: NL27WZ00 Dual 2- Input NAND Gate The NL27WZ00 is a high performance dual 2-input NAND Gate operating from a 1.65 V to 5.5 V supply. • • • • • • • • • • Extremely High Speed: tPD 2.4 ns typical at VCC = 5 V Designed for 1.65 V to 5.5 V VCC Operation
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NL27WZ00
NL27WZ00
NC7WZ00
NL27WZ00/D
NC7WZ00
NL27WZ00US
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DM7413N
Abstract: No abstract text available
Text: co 5 p^. K&M National s Q co 5 in 2 o Sim Semiconductor DM5413/DM7413 Dual 4-Input NAND Gates with Schmitt Trigger Inputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent gates each of w hich perform s the logic NAND fun ction. Each input
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DM5413/DM7413
F/6502-1
tti-55
400S1
DM7413N
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Untitled
Abstract: No abstract text available
Text: JOT National ÆÆ Semiconductor 54LS133/DM74LS133 13-Input NAND Gate General Description This device contains one, 13-input gate that performs the logic NAND functions. Connection Diagram Dual-ln-Llne Package 16 1 I 2 15 14 3 13 4 5 _ _ 12 6 11 7 10 8
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54LS133/DM74LS133
13-Input
TL/F/9818-1
54LS133DMQB,
54LS133FMQB,
54LS133LMQB,
DM74LS133M
DM74LS133N
LS133
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Untitled
Abstract: No abstract text available
Text: o CM ÆM National Semiconductor 54F/74F20 Dual 4-Input NAND Gate General Description This device contains two independent gates, each of which performs the logic NAND function. Ordering Code: See Section 5 Logic Symbol Connection Diagrams IEEE/IEC Pin Assignment
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54F/74F20
54F/74F
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74LVC2G00
Abstract: 74LVC2G00DC 74LVC2G00DP 74LVC2G00GD 74LVC2G00GM 74LVC2G00GT JESD22-A114E MO-187
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 07 — 10 June 2008 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
74LVC2G00DC
74LVC2G00DP
74LVC2G00GD
74LVC2G00GM
74LVC2G00GT
JESD22-A114E
MO-187
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PDF
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Untitled
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 10 — 30 November 2011 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
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74LVC2G00
Abstract: 74LVC2G00DC 74LVC2G00DP 74LVC2G00GD 74LVC2G00GM 74LVC2G00GT sot1089 V2G00
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 09 — 8 June 2010 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
74LVC2G00DC
74LVC2G00DP
74LVC2G00GD
74LVC2G00GM
74LVC2G00GT
sot1089
V2G00
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74LVC2G00
Abstract: 74LVC2G00DC 74LVC2G00DP 74LVC2G00GM 74LVC2G00GT MO-187
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 05 — 4 September 2007 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
74LVC2G00DC
74LVC2G00DP
74LVC2G00GM
74LVC2G00GT
MO-187
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PDF
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Untitled
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 06 — 20 February 2008 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
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Untitled
Abstract: No abstract text available
Text: N T E ELECTRONICS INC b M 3 1 5 S c QQOaô'ï? TTM B i N T E 52E D HIGH THRESHOLD LOGIC) Expandable, Dual, 4-Inp ut NAND Gate 14-Lead DIP, See Dlag. 247 Expandable, 4-Input NAND Gate Input A1 Input A1 Input B1 Input B1 T - S3 - 13 -û I 14-Lead DIP, See Dlag. 247
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14-Lead
T-90-01
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PDF
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Marking code V7
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G00
74LVC2G00
Marking code V7
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