DTL TTL LOGIC Search Results

Contextual Info: 8T30 N,F DESCRIPTION PIN CONFIGURATION The 8T30 is a dual bi-directional bus interchange element that interfaces MOS and TTL data busses. Data can be exchanged in a half-duplex transmission mode from a “ party line” TTL/DTL bus to a MOS transceiver port and a TTL/DTL transceiver port.

AH0014C

Abstract: AH0015CD
Contextual Info: AH0014/AH0014C* DPDT, AH0015/AH0015C Quad SPST, AH0019/AH0019C* Dual DPST-TTL/DTL Compatible MOS Analog Switches General Description This series of TTL/DTL compatible MOS analog switches feature high speed with internal level shifting and driving. The package contains two monolithic integrated circuit

AH0015CD

Abstract: D14D AH0014 AH0014D DTL or TTL integrated logic circuits AH0015 AH0014C AH0015C AH0019 AH0019C
Contextual Info: AH0014 AH0014C DPDT AH0015 AH0015C Quad SPST AH0019 AH0019C Dual DPST-TTL DTL Compatible MOS Analog Switches General Description This series of TTL DTL compatible MOS analog switches feature high speed with internal level shifting and driving The package contains two monolithic integrated circuit

dtl logic gates

Abstract: ttl NAND gate circuit series inverter circuit diagrams 9000 ttl 930 series dtl ttl NAND gate with expander K 9008 TTL 7430 6 a 8 mic 4 pin mic circuit
Contextual Info: Logic Integrateci Circuits, MIC 9 0 0 0 Series TTL C irc u it F unctions Compatible w ith M IC 930 Series DTL and other TTL and DTL Series M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9012

MDU-4F-15

Abstract: MDU-4F-20 MDU-4F-25 MDU-4F-35 MDU-4F-40 MDU-4F-45 MDU-4F-50 4F45 J1101
Contextual Info: ü F asf Logic Multiple Digital Delay Units 14 pins DIP TTL Interfaced Features: • Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket. ■ 4 equal delay units/package. Specifications:

Contextual Info: :a s t Logic Pulse Width Discriminator SERIES: PWD-21 TTL Interfaced Features: • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket.

Contextual Info: data y^v delayW devicesYinc. ?asf Logic Multiple Digital Delay Units 14 pins DIP TTL Interfaced Features: • Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket. ■ 4 equal delay units/package.

AY31015D

Abstract: AY-3-1015D
Contextual Info: & AY31015D Microchip IJAR/T: UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER FEATURES DESCRIPTION • DTL and TTL compatible - no interfacing circuits required - drives one TTL load • Fully Double Buffered - eliminates need for system synchronization, facilitates high-speed operation

Contextual Info: Agilent 10529A Logic Comparator Dat a Sheet Inputs Input Threshold: 1.4V nominal 1.8V nominal with socket board , TTL or DTL compatible. Test IC Loading: Outputs driving Test IC inputs are loaded by 5 low-power TTL loads plus input of Reference IC. Test IC outputs are loaded by 2 low-power TTL loads.

4F10

Contextual Info: 7 a s f Logic Multiple Digital Delay Units 14 pins DIP TTL Interfaced Features: • Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket. ■ 4 equal delay units/package. Specifications:

Contextual Info: r a s i Logic Pulse Width DiSCriminatOr data ser|es PWD.21 delay W devicesYinc TTL Interfaced Features: • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P C. board space economy achieved.

24.000 mhz

Abstract: FMU-3-3R000M
Contextual Info: Frequency Multiplying Unit data SERIES: FMU-3 14 pins DIP TTL Interfaced delay devices; _ Features: • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

Contextual Info: data delay devicesYinc. EFasf Logic Multiple Digital Delay Units SERIES: MDU-4F 14 pins DIP TTL Interfaced Features: • Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket. ■ 4 equal delay units/package.

Contextual Info: Frequency Multiplying Unit SERIES: FMU-3 14 pins DIP TTL Interfaced data delay devices; inc. Features: • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

AH0015CD

Abstract: AH0014C AH0014CD AH0014D AH0015 AH0015C AH0019C
Contextual Info: Febmaiy 1995 AH0014/AH0014C* DPDT, AH0015/AH0015C Quad SPST, AH0019/AH0019C* Dual DPST-TTL/DTL Compatible MOS Analog Switches General Description This series o f TTL/D TL compatible MOS analog switches feature high speed with internal level shifting and driving.

AY-3-1015D

Abstract: 0X033 ay-3-1015duart
Contextual Info: T-75-37-05 AY31015D M icrochip UAR/T: UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER FEATURES DESCRIPTION • DTL and TTL compatible - no interfacing circuits required - drives one TTL load • Fully Double Buffered - eliminates need for system synchronization, facilitates high-speed operation

Contextual Info: Frequency Multiplying Unit dataXft&fc delay p SERIES: FMU-3 14 pins DIP devices;inc. TTL Interfaced Features: • Auto-insertable. ■ Completely Interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

Contextual Info: Frequency Doubling Unit SERIES: FDU-2 14 pins DIP TTL Interfaced data \Q £ \ delay devicesVmc. Features: Auto-insertable. Completely interfaced with TTL and DTL application. No external components required. P.C. board space economy achieved. Fits standard 14 pins DIP socket.

Contextual Info: Frequency Doubling Unit SERIES: FDU-2 14 pins DIP TTL Interfaced d e la y \a / devices? inc. Features:. • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

Contextual Info: EFasf Logic Multiple Digital SERIES: MDU-38F Delay Units 8 pins DIP TTL Interfaced data delay devices. inc. a n » «ir '¿«mi Features: • Auto-insertable. ■ Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 8 pins DIP socket.

AY-3-1015D

Abstract: AY-3-1015 AY31015D/D
Contextual Info: OATA COMMUNICATIONS .1 Nl RAI INSI RIJM[ NI AY-3-1015D UAR/T: Universal Asynchronous Receiver/Transmitter FEATURES • DTL and TTL compatible—no interfacing circuits required— drives one TTL load ■ Fully Double Buffered—eliminates need for system

Contextual Info: Frequency Doubling Unit SERIES: FDU-2 14 pins DIP TTL Interfaced Features:. • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved. ■ Fits standard 14 pins DIP socket.

Contextual Info: Frequency Doubling Unit SERIES: FDU-2 14 pins DIP TTL Interfaced data V/3\>, delay ^0 devices; Features:. • Auto-insertable. ■ Completely interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

MDU-4F-10

Abstract: MDU-4F-15 MDU-4F-20 MDU-4F-25 MDU-4F-30 MDU-4F-35 MDU-4F-40 MDU-4F-45 MDU-4F-50
Contextual Info: data delay devicesYinc. EFasf L o g ic Multiple Digital Delay Units SERIES: MDU-4F 14 pins DIP TTL Interfaced Features: Completely interfaced for TTL & DTL application. P.C. board space economy achieved. Fits standard 14 pins DIP socket. 4 equal delay units/package.