DOD15 Search Results

Contextual Info: S N 74AC T215 7 2K x 16 C A C H E A D D R E S S C O M PA R A TO R /D A TA RAM D3326, JANUARY 1990-REVlSED JUNE 1990 Fast A ddress to Match Delay . . . 20 ns Max FN PACKAGE TOP VIEW Totem -Pole and Open-Drain Match Outputs On-Chip Address/D ata Com parator

te disa 1202

Abstract: l286
Contextual Info: Final 80L286 Low-Power High-Performance Microprocessor with Memory Management and Protection Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • High-performance processor up to 13.3 times IAPX 86 when using the 16 MHz 80L286 Surface-m ountable PLCC for high density

SN54299

Abstract: LG 21 fs 4
Contextual Info: TLC32044M VOICE-BAND ANALOG INTERFACE CIRCUIT D3495, MAY 1990 Advanced LinCMOS Sllicon-Gate Process Technology J PACKAGE TOP VIEW 14-Bit Dynamic Range ADC and DAC * * * * * * * 16-Bit Dynamic Range Input With Programmable Gain NU[ 1 RESETI 2 e o d r Variable ADC and DAC Sampling Rate up to

tlr2u

Contextual Info: H D4 04 4 1 8 /H D4 07 4 41 8 / H D4074408 D e sc rip tio n T he HD404418, HD4074418, a n d H D 4074408 a re 4-b it sin g le-ch ip m ic ro c o m p u te rs b a s i­ cally e q u iv a le n t to th e HM CS400 se rie s p ro ­ vid in g h ig h p ro g ra m m in g p ro d u c tiv ity a n d

Contextual Info: #U179 HD4074408, HD4074418 HMCS400 SERIES ZTAT MICROCOMPUTER JANUARY, 1988 0 HITACHI Description The HD404418, HD4074418, and HD4074408 are 4-bit single chip m icrocomputers basically equivalent to th e HMCS400 series providing high program m ing productivity and high­

Contextual Info: in te i 386 DX MICROPROCESSOR HIGH PERFORMANCE 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus

CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip

Abstract: CT2500 CT1698 mil-std-1397
Contextual Info: CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip Features • Performs Source and Sink functions CIRCUIT TECHNOLOGY www.aeroflex.com • Implements Type D & E protocols • Burst Mode Capability A E RO • Available in a PGA Package

MAKING CODE 1H sod

Contextual Info: TMS34094 ISA BUS INTERFACE S PV S 006A - FEBRUARY 1992 - REVISED JUNE 1992 • Simplifies Design of High-Performance ISA PC Graphics Systems • Single-Integrated Circuit Interfaces TMS34020 to ISA Bus • Conforms to ISA Portions of the EISA Rev. 3.11 Specifications

hynix HYMD264646B8J-D43

Abstract: HYMD264646b8j-d43
Contextual Info: 64Mx64 bits Unbuffered DDR SDRAM DIMM HYMD264646B8J DESCRIPTION Hynix HYMD264646B8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules DIMMs which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD264646B8J series consists of

11-CQ2

Contextual Info: IBM13N4649JC IBM13N4739JC PRELIMINARY 4M X 64/72 2 Bank Unbuffered SDRAM Module Features • 168 Pin emerging JEDEC Standard, Unbuffered Byte Dual In-line Memory Module • 4Mx64/72 Synchronous DRAM DIMM • Performance: CAS Latency fcK Clock Frequency tcK

TS68008CP8

Abstract: 24182 ef9367 EF6850 SN74LS73 SG 6CA SH 05.22 48-PIN A0-A21 TS68000
Contextual Info: ^ S C S -T H O M S O N D g l( e m i( g T [ R M O ( g S T S 6 8 0 0 8 8/16-B IT MICROPROCESSOR WITH 8-B IT DATA BUS • ■ ■ ■ ■ ■ ■ 17 32-BIT DATA AND ADDRESS REGISTERS 56 BASIC INSTRUCTION TYPES EXTENSIVE EXCEPTION PROCESSING MEMORY MAPPED I/O

delco dm 8

Abstract: DD-03282PP Delco IC receivers DM-466
Contextual Info: d Td Tc DD-03282 ARINO 429 TRANSCEIVER IL.C D A T A D E V IC E CORPORATION — FEATURES DESCRIPTION The DD-03282 device is a two-channel receiver, one-channel transmitter in accordance with the “ARINC Specifi­ cation 429 Digital Information Transfer System, Mark 33” ARINC 429 . This

Contextual Info: .,f,i . . ,.:.:,;ri, ,.:. , ,.:,+:. . . . .4., ? >.,“ .s, ,. .,. ., c .,. , ,. $ ., ,. . ., s ., .,., ! .,.,.,. : .”,>. . . . . . . . . ,., , . . . . . . . . ., ., , .,., , . . . . Order this document Freescale Semiconductor, Inc.

hymd564646b8j-d43

Abstract: HYMD532646B6-H DDR400B DDR266 DDR266B DDR333 DDR400 hynix module suffix hynix module suffix 184pin HYMD532646BP6
Contextual Info: 184pin Unbuffered DDR SDRAM DIMMs based on 512Mb B ver. This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 512Mb B ver. DDR SDRAMs in 400mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered DIMM series provide

mcm6830

Abstract: EXORCISER motorola M68MM01A 7642T MC68B54 transistor bf 175 motorola application note 6809 6844 MMS1117 EXORCISER motorola M68MM01A2
Contextual Info: The MS800MM0S Support Elem ents Other NMOS MPUs MC3870 ^ MICROCOMPUTER COMPONENTS CMOS MCUS/ICUS MC14S00B, MC141000/1206 Bipolar 4-Blt slice MPU Fam ilies M2900 TTL , M10800 (MECL) nm os Memories RAM, EPROM, ROM CMOS Memories RAM, ROM MEMORY PRODUCTS Bipoiar Memories

Contextual Info: 184pin Unbuffered DDR SDRAM DIMMs based on 512Mb C ver. TSOP This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR SDRAMs in 400mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb C ver. based unbuffered DIMM series provide

Contextual Info: 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb 1st ver. This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based DDR2 Unbuffered DIMM

8089 microprocessor pin diagram

Abstract: 8089 microprocessor block diagram 8089 intel microprocessor Architecture Diagram 8089 microprocessor architecture 2142 RAM 8284 intel microprocessor architecture input output processor 8089 multiprocessor 8089 8080a intel microprocessor Architecture Diagram communication between cpu and iop
Contextual Info: In te l 8089 8 & 16-BIT HMOS I/O PROCESSOR High Speed DMA C apabilities Including I/O to Memory, M em ory to I/O, M em ory to Memory, and I/O to I/O iAPX 86, 88 Com patible: Removes I/O Overhead from CPU in iAPX 86/11 or 88/11 Configuration Mem ory Based Communication with

Contextual Info: 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646B L F8-J/M/K/H/L Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History No. History Draft Date 0.1 Initial Draft Jan. 2004 0.2 IDD3P Value Adjusted from 216 to 192 [mA] at Page 9 Apr. 2004 Remark

Contextual Info: 184pin Unbuffered DDR SDRAM DIMMs based on 256Mb D ver. TSOP This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400 mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based unbuffered DIMM series provide

hynix ddr2 ram

Abstract: HYNIX DDR2 512M hynix hy5ps1g
Contextual Info: 240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb M version This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 2Gb M version DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb version M based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm

74LS45

Abstract: DRAM 4464 uses of 74ls245 to speed up buses tms 4464 10BASE-7 NQ8005 logic diagram of 74LS245 4464 dram ns-1a 0.1 ohm 1.0% 74LS245
Contextual Info: 8005 Advanced Ethernet Data Link Controller AEDLC June 1991 Features • C o n fo rm s to IE E E 802.3 S ta n d a rd • E th e rn e t (10BASE-5) C heapernet (10BASE-2) a n d T w isted P a ir (10BASE-T) ■ R ecognizes One to S ix Selectable S tation

XC-01

Abstract: D70236 smd 3F9 uPD72291 JUPD70236 interfacing of 8251 devices with 8085 high level language programming of 8085 microprocessor 8085 mnemonic opcode ls-112 TFK U 111 B
Contextual Info: NEC Electronics Inc. Description The V53 is a high-speed, high-integration 16-bit CM O S m icroprocessor with a CPU that is object and source code com patible with the V20 /V30®. Integrated on the same die is a 4-channel D M A controller, a DART, three

Contextual Info: 240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 2Gb A version DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb version A based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm