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    DDR SDRAM 128MBIT 8MX16 Search Results

    DDR SDRAM 128MBIT 8MX16 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AT25SF128A-SHBHD-T Renesas Electronics Corporation 128Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O Support Visit Renesas Electronics Corporation
    AT25SF128A-SHB-T Renesas Electronics Corporation 128Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O Support Visit Renesas Electronics Corporation
    AT25SF128A-MHB-T Renesas Electronics Corporation 128Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O Support Visit Renesas Electronics Corporation
    AT25QF128A-MHB-T Renesas Electronics Corporation 128Mbit, 3V SPI Serial Flash Memory with Dual I/O and Quad I/O Support Visit Renesas Electronics Corporation
    AT25QF128A-SHBHD-T Renesas Electronics Corporation 128Mbit, 3V SPI Serial Flash Memory with Dual I/O and Quad I/O Support Visit Renesas Electronics Corporation

    DDR SDRAM 128MBIT 8MX16 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HY5MS5B6BLFP

    Abstract: HY5MS5B6BL
    Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M 8Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for


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    PDF 128Mbit 8Mx16bit) 128Mbit 16bit) H5MS1262EFP 16bits) HY5MS5B6BLFP HY5MS5B6BL

    hynix mcp

    Abstract: HY5MS5B6BL H5MS1262EFP 2Mx16
    Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M 8Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for


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    PDF 128Mbit 8Mx16bit) 128Mbit 16bits) 16bit) H5MS1262EFP 00Typ. hynix mcp HY5MS5B6BL 2Mx16

    JESD-21C

    Abstract: No abstract text available
    Text: PC1600 and PC2100 DDR SDRAM Unbuffered DIMM Design Specification Revision 1.1 October 15, 2001 Table of Contents PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification Table of Contents Table of Contents .2


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    PDF PC1600 PC2100 PC1600/PC2100 JC-42 JESD-21C

    PC1600U-25330-B1

    Abstract: JESD-21C JESD21 ddr dimm pinout ddr sdram 128Mbit 8Mx16 PC2100 32MX7
    Text: PC1600 and PC2100 DDR SDRAM Unbuffered DIMM Design Specification Revision 1.1 June 29, 2001 Table of Contents PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification Table of Contents Table of Contents .2


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    PDF PC1600 PC2100 PC1600/PC2100 JC-42 PC1600U-25330-B1 JESD-21C JESD21 ddr dimm pinout ddr sdram 128Mbit 8Mx16 32MX7

    sdram pcb layout gerber

    Abstract: ddr sdram 128Mbit 8Mx16 pc133 sdram 512mb ECC unbuffered pc133 SDRAM DIMM PC133 SDRAM Unbuffered DIMM trace code micron label PC200U-25330B-1 JC42 sdram pc133 pcb layout guide micron sdram pc133 pcb layout guide
    Text: DDR SDRAM Unbuffered DIMM Design Specification Revision 0.6 November 1999 JC-42.5 Item #:_ Prepared By Micron Technology and IBM DDR SDRAM Unbuffered DIMM Design Specification Page 2 Revision 0.6 DDR SDRAM Unbuffered DIMM Design Specification Table of Contents


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    PDF JC-42 sdram pcb layout gerber ddr sdram 128Mbit 8Mx16 pc133 sdram 512mb ECC unbuffered pc133 SDRAM DIMM PC133 SDRAM Unbuffered DIMM trace code micron label PC200U-25330B-1 JC42 sdram pc133 pcb layout guide micron sdram pc133 pcb layout guide

    512MB 8Mx32 DDR DRAM

    Abstract: No abstract text available
    Text: SU5320835D4F0CU August 19, 2004 Ordering Information Part Numbers Description Module Speed SM5320835D4F0CG 8Mx32 32MB , DDR, 100-pin DIMM, Unbuffered, Non-ECC, 8Mx16 Based, DDR266A, 25.40mm, 22Ω DQ termination. PC2100 @ CL 2.0, 2.5 SB5320835D4F0CG 8Mx32 (32MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,


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    PDF SU5320835D4F0CU SM5320835D4F0CG SB5320835D4F0CG 8Mx32 100-pin 8Mx16 DDR266A, 512MB 8Mx32 DDR DRAM

    Untitled

    Abstract: No abstract text available
    Text: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)


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    PDF IS43R16800CC 8Mx16 128Mb 66-pin IS43R16800CC-5TLI IS43R16800CC-6TLI IS43R16800CC-75TLI

    Untitled

    Abstract: No abstract text available
    Text: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM JUNE 2009 FEATURES: DESCRIPTION: •฀ VDD =VDDQ = 2.5V+0.2V -5, -6, -75 •฀ Double data rate architecture; two data transfers per clock cycle. •฀ Bidirectional , data strobe (DQS) is transmitted/ received with data


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    PDF IS43R16800CC 8Mx16 128Mb IS43R16800CC-6TL 66-pin IS43R16800CC-5TLI IS43R16800CC-6TLI

    IS43R16800CC

    Abstract: 43R16800CC A3S56D zentel ddr sdram 128Mbit 8Mx16 40ETP
    Text: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)


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    PDF IS43R16800CC 8Mx16 128Mb IS43R16800CC-6TL 66-pin IS43R16800CC-5TLI IS43R16800CC-6TLI IS43R16800CC 43R16800CC A3S56D zentel ddr sdram 128Mbit 8Mx16 40ETP

    R362B

    Abstract: R113B C307B C245B C268B r272b CONN-HEADER 3 pos u78b gp741 BT 217
    Text: Intel PXA26x Processor Family Design Guide — Revision 1.0 October 2002 Order Number: 278639-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN


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    PDF PXA26x nPIOIS16 09Sept02 DCPXA26x DCPXA26x R362B R113B C307B C245B C268B r272b CONN-HEADER 3 pos u78b gp741 BT 217

    IS43R16800E

    Abstract: No abstract text available
    Text: IS43/46R16800E, IS43/46R32400E ADVANCED INFORMATION 4Mx32, 8Mx16 MAY 2011 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • • • • ISSI’s 128-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory


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    PDF IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb 128-Mbit 728-bit 16-bit 32-bit IS43R16800E

    IS43R32400E

    Abstract: IS43R32400E-5BLI IS43R16800E-6TL IS43R16800E
    Text: IS43/46R16800E, IS43/46R32400E MARCH 2012 4Mx32, 8Mx16 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/


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    PDF IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb 60-Ball) IS43R32400E IS43R32400E-5BLI IS43R16800E-6TL IS43R16800E

    IS43R16800E

    Abstract: IS43R32400E-5BLI
    Text: IS43/46R16800E, IS43/46R32400E FEBRUARY 2013 4Mx32, 8Mx16 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/


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    PDF IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb 60-Ball) IS43R16800E IS43R32400E-5BLI

    IS43R16800E

    Abstract: No abstract text available
    Text: IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb DDR SDRAM FEBRUARY 2013 FEATURES DEVICE OVERVIEW •฀ VDD฀and฀VDDQ:฀2.5V฀±฀0.2V฀ •฀ SSTL_2฀compatible฀I/O •฀ Double-data฀rate฀architecture;฀two฀data฀transfers฀ per clock cycle


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    PDF IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb 60-Ball) IS43R16800E

    IS43R16800E

    Abstract: DDR SDRAM
    Text: IS43/46R16800E, IS43/46R32400E JANUARY 2014 4Mx32, 8Mx16 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • • • • ISSI’s 128-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory


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    PDF IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 128Mb 128-Mbit 728-bit 16-bit 32-bit IS43R16800E DDR SDRAM

    Untitled

    Abstract: No abstract text available
    Text: IS43R16800D, IS43R32400D PRELIMINARY INFORMATION 4Mx32, 8Mx16 MARCH 2009 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/ received with data, to be used in capturing data


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    PDF IS43R16800D, IS43R32400D 4Mx32, 8Mx16 128Mb IS43R32400D-4BLI IS43R32400D-5BLI IS43R32400D-6BLI 144-ball

    Untitled

    Abstract: No abstract text available
    Text: IS43R16800D, IS43R32400D PRELIMINARY INFORMATION 4Mx32, 8Mx16 SEPTEMBER 2008 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/ received with data, to be used in capturing data


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    PDF IS43R16800D, IS43R32400D 4Mx32, 8Mx16 128Mb

    issi 8Mx16 SDRAM

    Abstract: ISSI 346
    Text: IS43R16800D, IS43R32400D PRELIMINARY INFORMATION 4Mx32, 8Mx16 JULY 2009 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/ received with data, to be used in capturing data


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    PDF IS43R16800D, IS43R32400D 4Mx32, 8Mx16 128Mb 144-ball IS43R32400D-4BLI IS43R32400D-5BLI IS43R32400D-6BLI issi 8Mx16 SDRAM ISSI 346

    Untitled

    Abstract: No abstract text available
    Text: IS43LR16800D, IS43LR32400D 4Mx32, 8Mx16 128Mb Mobile DDR SDRAM FEATURES: • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe DQS is transmitted/ received with data, to be used in capturing data at the receiver


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    PDF IS43LR16800D, IS43LR32400D 4Mx32, 8Mx16 128Mb IS43LR32400D-5BL IS43LR32400D-6BL IS43LR32400D-75BL 90-ball

    822AT

    Abstract: No abstract text available
    Text: 3rd 128M DDR SDRAM HY5DU28422AT HY5DU28822AT HY5DU281622AT Revision 1.3 April 2001 This docum ent is a general product description and is subject to change without notice. HY5DU28422AT/822AT/1622AT 128Mb x4, x8, x16 Double Data Rate SDRAM PRELIMINARY D ESC R IPTIO N


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    PDF HY5DU28422AT HY5DU28822AT HY5DU281622AT HY5DU28422AT/822AT/1622AT 128Mb HY5DU28422, HY5DU28822 HY5DU281622 728-bit 822AT

    urst 1081

    Abstract: No abstract text available
    Text: 2nd 128M DDR SDRAM HY5DU28422T HY5DU28822T HY5DU281622T Revision 1.3 April 2001 This document is a general product description and is subject to change without notice. 289 HY5DU28422T/822T/1622T 128Mb x4, x8, x16 Double Data Rate SDRAM PRELIMINARY D E S C R IP T IO N


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    PDF HY5DU28422T HY5DU28822T HY5DU281622T HY5DU28422T/822T/1622T 128Mb 728-b Y5DU28422T/822T/1622T 128M-bit urst 1081

    hy57v168010b

    Abstract: ddr sdram 128Mbit 8Mx16 54-PIN
    Text: SDRAM ORDERING INFORMATION 4Mbit SDRAM Cttöanfeattws 256Kx16 Bank 2 1K Bank 2 2 2 Ref. 4K 4K 4K PWtNO» HY57V16401ÛBTC HY57V168010BTC HY57V161610BTC Bänk 2 2 2 Ref. PW Ho. 4K HY57V16401ÛCTC 4K HY57V168010CTC 4K HY57V161610CTC ii/ k - Pm N o. M ax.im x


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    PDF 256Kx16 HY57V41610TC 400mil 16Mbit 1Mx16 HY57V16401 HY57V168010BTC HY57V161610BTC 44pin) hy57v168010b ddr sdram 128Mbit 8Mx16 54-PIN

    W25X128

    Abstract: W25Q40 w25q64 W25Q16BW W25Q64bv W25X80BV W25Q32BV W25016BV winbond* W25Q W25X16AV
    Text: winband We D eliv er 2009 Product Selection Guide Mobile RAM Specialty DRAM Flash Memory Memory Product Foundry Service O W Product Selection Guide 2009 » Contents 2 Mobile RAM Pseudo SRAM Low Power SDR SDRAM Low Power DDR SDRAM 4 Specialty DRAM SDRAM DDR SDRAM


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    PDF 300mm W25X128 W25Q40 w25q64 W25Q16BW W25Q64bv W25X80BV W25Q32BV W25016BV winbond* W25Q W25X16AV

    winband

    Abstract: W25X40BV W25Q408W w25x40v W651GG2JB WSON* 8x6mm w25q128 W25X16AV 208-MIL w25X20BV
    Text: t/vinband We D eliver Product Selection Guide - o 2010 Mobile RAM Specialty DRAM Graphics DRAM Flash Memory Memory Product Foundry Service Product Selection Guide 2010 Contents 2 Mobile RAM Pseudo SRAM Low Power SDR SDRAM Low Power DDR / DDR2 SDRAM


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    PDF 300mm winband W25X40BV W25Q408W w25x40v W651GG2JB WSON* 8x6mm w25q128 W25X16AV 208-MIL w25X20BV