DATA INPUT Search Results

Contextual Info: INTEGRATED CIRCUITS - TTL TRANSISTOR TRANSISTOR LOGIC NTE74150 24-Lead DIP, See Diag. 252 1—of—16 Data Selector/Multiplexer I E E Data Inpu Data Inpu V cc Data Inpu Output EO Data Inpu 4 | Q Output GS Data Inpu input 3 Data inpu Q Input 2 Data Jnpu Output AO

NTE7404

Abstract: NTE7408 NTE7407 NTE7406 NTE7400 NTE74LS04 NTE74HC04 NTE74LS08 NTE74HC08 NTE74LS00
Contextual Info: INTEGRATED CIRCUITS - TTL TRANSISTOR TRANSISTOR LOGIC NTE7214 16-Lead DIP, See Diag. 249 TRI-STATE Dual 4:1 Multiplexer Strobe 1G V CC B Address Strobe 2G Data Input Q A Address Data Input Data Input Data Input Data Input Data Input Q Data Input Output 1Y

Contextual Info: INTEGRATED CIRCUITS - TTL TRANSISTOR TRANSISTOR LOGIC NTE7214 16-Lead DIP, See Diag. 249 TRI-STATE Dual 4:1 Multiplexer Strobe 1G VCC B Address Strobe 2G Data Input Q A Address Data Input Data Input Data Input Data Input Data Input Q Data Input 14-Lead DIP, See Diag. 247

double through put multiply accumulate

Abstract: arithmetic logic unit datasheet 8 BIT ALU Dynamic arithmetic shift DSP56K "saturation arithmetic"
Contextual Info: SECTION 3 DATA ARITHMETIC LOGIC UNIT MOTOROLA DATA ARITHMETIC LOGIC UNIT 3-1 SECTION CONTENTS SECTION 3.1 DATA ARITHMETIC LOGIC UNIT . 3 SECTION 3.2 OVERVIEW AND DATA ALU ARCHITECTURE . 3 3.2.1 Data ALU Input Registers X1, X0, Y1, Y0 . 5

Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)

hynix lpddr2

Abstract: ELPIDA mobile dram LPDDR2 Elpida LPDDR2 Memory hynix lpddr2 sdram lpddr2 DQ calibration Hynix 4Gb LPDDR2 LPDDR2 SDRAM hynix NT6TL64M32AQ -G1 lpddr2-s2 LPDDR2 1Gb Memory
Contextual Info: 2Gb LPDDR2-S4 SDRAM NT6TL64M32AQ Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS, /DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)

LVDS Serializer

Contextual Info: 19-3955; Rev 1; 9/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer The MAX9247 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial-data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial-data rate. The data-enable input determines

MAX9217

Abstract: MAX9217ECM MAX9217ETM MAX9218 IC-2526
Contextual Info: 19-3558; Rev 4; 8/09 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines

lcd 40 pin diagram lvds

Abstract: LVDS Serializer HSYNC, VSYNC input output MAX9217 MAX9217ECM MAX9217ETM MAX9218
Contextual Info: 19-3558; Rev 3; 5/08 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines

74ALS157

Abstract: 74ALS157N 74ALS 74ALS157D 74ALS158 74ALS158D 74ALS158N
Contextual Info: INTEGRATED CIRCUITS 74ALS157/74ALS158 Data selector/multiplexer Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Data selector/multiplexer 74ALS157/74ALS158 74ALS157 Quad 2-input data selector/multiplexer, non-inverting

74151A multiplexers

Abstract: 74151A 75151A DM74150N DM54151A 74150 54151A 54150FMQB DM54150J DM74150
Contextual Info: DM74150, DM74151A Data Selectors/Multiplexers General Description Features These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The 150 selects one-of-sixteen data sources; the 151A selects one-of-eight data sources. The 150 and 151A have a strobe input which

74als257

Abstract: 74ALS 74ALS257D 74ALS257DB 74ALS257N 74ALS258 74ALS258D 74ALS258DB ya 11
Contextual Info: INTEGRATED CIRCUITS 74ALS257/74ALS258 Data selector/multiplexer Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Data selector/multiplexer 74ALS257/74ALS258 74ALS257 Quad 2-input data selector, non-inverting 3-State

KPB datasheet

Abstract: RP-125 CCIR624-3
Contextual Info: PI-003 PARALLEL DATA TO CVBS 10 BIT INPUT Parallel multiplexed component signals to CCIR Rec 656 SMPTE RP-125 coded. Note. To ease interfacing into equipment data is latched by the rising edge of the clock. Data rate Data Set up time Data hold time Line standard

KPB datasheet

Abstract: RP-125 CCIR624-3
Contextual Info: PI-003 PARALLEL DATA TO CVBS 10 BIT INPUT Parallel multiplexed component signals to CCIR Rec 656 SMPTE RP-125 coded. Note. To ease interfacing into equipment data is latched by the rising edge of the clock. Data rate Data Set up time Data hold time Line standard

Contextual Info: 74AUP1G157 Low-power 2-input multiplexer Rev. 5 — 22 June 2012 Product data sheet 1. General description The 74AUP1G157 is a single 2-input multiplexer which selects data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74AUP2G157 Low-power 2-input multiplexer Rev. 6 — 6 June 2012 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74AUP1G157

Abstract: 74AUP1G157GF 74AUP1G157GM 74AUP1G157GW
Contextual Info: 74AUP1G157 Low-power 2-input multiplexer Rev. 3 — 28 October 2010 Product data sheet 1. General description The 74AUP1G157 is a single 2-input multiplexer which selects data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74AUP1G157 Low-power 2-input multiplexer Rev. 5 — 22 June 2012 Product data sheet 1. General description The 74AUP1G157 is a single 2-input multiplexer which selects data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 6 — 31 December 2012 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74LVC1G157GW

Abstract: 74LVC1G157 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV JESD22-A114E
Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 03 — 12 July 2007 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74AUP2G157 Low-power 2-input multiplexer Rev. 7 — 18 January 2013 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74AUP2G157DC

Abstract: 74AUP2G157GT
Contextual Info: 74AUP2G157 Low-power 2-input multiplexer Rev. 4 — 30 July 2010 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74LVC1G157

Abstract: 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV 74LVC1G157GW
Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 4 — 28 October 2010 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 5 — 6 December 2011 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data