DATA CHIP 555 Search Results

AHA3101

Abstract: A3101 d2553 aha3101a020pqc AHA3210 M 3101 aha3101a
Contextual Info: Advanced Hardware Architectures, Inc. 1.0 INTRODUCTION_ The AHA3101 Data Compression chip provides the basis for a complete data compression system. The chip uses an external static RAM chip, to store compression information, and also to buffer data.The chip is fabricated in a CMOS process, and

Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

dts master audio DL 1200

Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

dts master audio DL 1200

Abstract: ADSP-21365 CP-1201 Dolby prologic IIx decoder
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

hFFFFFFFF

Contextual Info: Section 20 RAM 20.1 Overview The SH7040 series has 4 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller DMAC /data transfer controller (DTC) with a 32-bit data bus (figure 20.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The DMAC

LQW18CN85

Abstract: LQW18C LQW18CNR33J00
Contextual Info: Inductors coils /Microchip Transformer > Chip Inductor (Chip Coil) > Power Inductor (Wire Wound Type for Choke) Data Sheet Chip Inductor (Chip Coil) 1 Power Inductor (Wire Wound Type for Choke) LQW18C Series (0603 Size) • Packaging 0.2±0.1 0.8±0.2 ■ Dimensions

LQW18CNR47J00

Abstract: LQW18CNR65J00 LQW18CNR33j LQW18CN55NJ00P 10MHZ LQW18CN85 LQW18CNR12J00 LQW18CN33NJ 1380MHz 330nh inductor coil
Contextual Info: Inductors Coils > Chip Inductor (Chip Coil) > Power Inductor (Wire Wound Type for Choke) Data Sheet 1 Chip Inductor (Chip Coil) Power Inductor (Wire Wound Type for Choke) LQW18C Series (0603 Size) c Packaging Code Packaging Minimum Quantity D 180mm Paper Tape

8 channel audio amplifier circuit diagram

Abstract: SKE 1/16 ANDO AF-9703 PDF DETAILS ske 1/17 AF 9704 32 pin dot matrix lcd AF-9703 555 Timer Voltage-Controlled Oscillator Circuit IC-3401 P1D3
Contextual Info: DATA SHEET DATA SHEET MOS INTEGRATED CIRCUIT mPD17012 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION The µPD17012 is a 4-bit single-chip CMOS microcontroller containing hardware ideal for organizing a digital tuning

AS17012

Abstract: LCD15
Contextual Info: DATA SHEET DATA SHEET MOS INTEGRATED CIRCUIT mPD17012 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION The µPD17012 is a 4-bit single-chip CMOS microcontroller containing hardware ideal for organizing a digital tuning

TTC 103

Abstract: PLCC44 T89C51CC01 TQFP44 80C51 12MHz osc
Contextual Info: 1. Features • 80C51 core architecture: – 256 bytes of on-chip RAM – 1 Kbytes of on-chip ERAM – 32 Kbytes of on-chip Flash memory Data Retention: 10 years at 85°C Read/Write cycle: 10k – 2 Kbytes of on-chip Flash for Bootloader – 2 Kbytes of on-chip EEPROM

object counter

Abstract: object counter circuit 80C51 PLCC44 T89C51CC01 VQFP44
Contextual Info: 1. Features • 80C51 core architecture: – 256 bytes of on-chip RAM – 1 Kbytes of on-chip ERAM – 32 Kbytes of on-chip Flash memory Data Retention: 10 years at 85°C Read/Write cycle: 10k – 2 Kbytes of on-chip Flash for Bootloader – 2 Kbytes of on-chip EEPROM

at89c51cc03 code examples

Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

89C51CC03UA

Abstract: 89c51cc03ca-Im VQFP-44 TTC 103 at89c51cc03 parallel programmer 80C51 AT89C51CC03 PLCC44 PLCC52 VQFP44
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

at89c51cc03 parallel programmer

Abstract: at89c51cc03 code examples ccf um 80C51 AT89C51CC03 PLCC44 PLCC52 VQFP44 VQFP64 BIPOLAR MEMORY
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

Contextual Info: a SHARC Processor ADSP-21362 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance automotive audio processing Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM

89C51CC03UA

Abstract: 89C51CC03CA-UM 89C51CC03UA-UM VQFP64 AT89C51CC03UA-RLTUM at89c51cc03 parallel programmer 80C51 AT89C51CC03 PLCC44 PLCC52
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

IDT20

Abstract: at89c51cc03 code examples 4182H
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

80C51

Abstract: AT89C51CC03 PLCC44 PLCC52 VQFP44 VQFP64 4182N 89C51CC03CA-UM
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

80C51

Abstract: AT89C51CC03 PLCC44 PLCC52 VQFP44 VQFP64 at89c51cc03 code examples AT89C51CC03C
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

89C51CC03UA-um

Abstract: 89C51CC03CA-UM at89c51cc03 parallel programmer AT89C51CC03UA-RDTUM AT89C51CC03UA-SLSUM 80C51 AT89C51CC03 PLCC44 PLCC52 VQFP44
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

89C51CC03CA-UM

Abstract: AT89C51CC03CA-RDTUM at89c51cc03 code examples IDT20 89C51CC03UA-um
Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM

Contextual Info: Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM