DADA SHEET Search Results

ARM1136

Abstract: metrowerks codetest ARM11 Smartphone display driver
Contextual Info: Reducing Time to Market: Parallel Software Development with Emulation and Simulation Tools for Mobile Extreme Convergence MXC Architectures By Gerardo A. Dada CONTENTS 1.0 Introduction . 2 2.0 Freescale’s MXC Architecture. 2

28BYJ48

Abstract: 28byj-48 i2c/Darlington Transistor Array
Contextual Info: Raspberry Pi - SPISPI-ADAD-DADA-& I2C 11-Wire Board Support Raspberry Pi-V2 P5 , got extra 4 GPIO 28,29,30,31 The 1-Wire port is based around a DS2482-100 I2C to 1-Wire bridge device. The DS2482-100 provides bi-directional protocol conversion between the I2C port on the

Contextual Info: 13 12 10 NOTES: 1. M ATERIALS: HOUSING - LIQUID C R YSTA L POLYMER LCP , BLACK, U L 94 V -0 TERN INALS - HIGH PERFORMANCE COPPER ALLOY 2. FINISH: SELEC TIVE 3 0 K GOLD IN CONTACT AR EA WITH LUBE. SELEC TIVE TIN /LEA D OR SELEC TIVE TIN ON PCB TAILS. NICKEL U N D ER PLATE O VERALL.

YCL Electronics

Abstract: adsl filter MF601HK Dada sheet
Contextual Info: Product Specification MF601HK File No RDPS-MF034 Revision R0 System Application Product Type Asymmetric Digital Subscriber Line Micro Filter for ADSL CPE SIDE Product Name MF601HK Date Issued By Jan . 03th, 2002 Bert Lin - Design Engineer, R&D_1 bert@ycl.com.tw

MSM5117405D

Abstract: MSM5117405D-50 MSM5117405D-60 MSM5117405D-70 D-50 MSM5117405
Contextual Info: Semiconductor This version:Apr.1999 MSM5117405D 4,194,304-Word ´ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5117405D is a 4,194,304-word ´ 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5117405D achieves high integration, high-speed operation, and low-power consumption

MB87077

Abstract: MB87077P MB87077PF
Contextual Info: August 1992 Edition 2.0A FUJITSU DATA SHEET M B87077 6-bit, 4-channel Electronic Volume Controller The Fujitsu MB87077 is a 6-bit, 4-channel electronic volume controller. A digital signal input controls gain every 0.5 dB step from OdB to -32dB. K has been fabricated in

DAAM

Contextual Info: ISL9011 Data Sheet March 13, 2006 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from channel 1 and 300mA from channel 2. The device has a low standby current and highPSRR and is stable with output capacitance of 1µF to 10µF

ISL9011

Abstract: ISL9011IRMMZ ISL9011IRMNZ ISL9011IRNCZ ISL9011IRNFZ ISL9011IRNJZ ISL9011IRNNZ MIC2211
Contextual Info: ISL9011 Data Sheet June 21, 2006 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from channel 1 and 300mA from channel 2. The device has a low standby current and highPSRR and is stable with output capacitance of 1µF to 10µF

ldo pinout

Abstract: ISL9011 ISL9011IRMMZ ISL9011IRMNZ ISL9011IRNCZ ISL9011IRNFZ ISL9011IRNJZ ISL9011IRNNZ MIC2211 dyaa
Contextual Info: ISL9011 S ESIGN EW D ART N R D FO NT P ENDE PLACEME M M O RE EC Data Sheet NOT R MMENDED 9011A L O S I REC March 10, 2008 Dual LDO with Low Noise, Low IQ and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from Channel 1 and 300mA from

Contextual Info: ISL9011 S ESIGN EW D ART N R D FO NT P ENDE PLACEME M M O RE EC Data Sheet NOT R MMENDED 9011A L O S I REC March 10, 2008 Dual LDO with Low Noise, Low IQ and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from Channel 1 and 300mA from

ldo pinout

Abstract: ISL9011 ISL9011IRMNZ ISL9011IRNCZ ISL9011IRNFZ ISL9011IRNJZ ISL9011IRNNZ ISL9011IRVVZ MIC2211 dyAA
Contextual Info: ISL9011 Data Sheet October 13, 2005 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from channel 1 and 300mA from channel 2. The device has a low standby current and highPSRR and is stable with output capacitance of 1µF to 10µF

DFN 3x3

Abstract: Capacitor 47uf 25v E2-5 DFN PACKAGE thermal resistance intersil PART MARKING intersil standard part marking MO-229 ISL9011 ISL9011IRMNZ ISL9011IRNCZ ISL9011IRNFZ
Contextual Info: ISL9011 Data Sheet December 20, 2005 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9011 is a high performance dual LDO capable of sourcing 150mA current from channel 1 and 300mA from channel 2. The device has a low standby current and highPSRR and is stable with output capacitance of 1µF to 10µF

MSM514265ESL

Abstract: MSM514265E PEDD514265ESL-01
Contextual Info: PEDD514265ESL-01 This version : Jan. 2001 Semiconductor MSM514265E/ESL Preliminary 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM514265E/ESL is a 262,144-word x 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS

MSM5117805

Abstract: MSM5117805D
Contextual Info: Semiconductor This version:Apr.1999 MSM5117805D 2,097,152-Word ´ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5117805D is a 2,097,152-word ´ 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5117805D achieves high integration, high-speed operation, and low-power consumption

Contextual Info: NT5DS64M8DS N2DS51216DS Preliminary 512Mb DDR SDRAM Feature CAS Latency Frequency  2KB page size for all configurations. DDR-333 DDR400 -6K -5T 2.5-3-3 3-3-3 CL=2 266 266 CL=2.5 333 333 CL=3 333 400 Speed Sorts Units  DQS is edge-aligned with data for reads and is

Contextual Info: N2DS25680DS N2DS25616DS Preliminary 256Mb DDR SDRAM  Feature CAS Latency Frequency DDR-333 center-aligned with data for WRITEs DDR400 Speed Sorts -5T 2.5-3-3 3-3-3 CL=2 266 266 CL=2.5 333 333 CL=3 333 400 CL-tRCD-tRP Speed  Units -6K  Differential clock inputs CK and 

NT5DS32M16

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts

sunplus camera

Abstract: sunplus USB OV7610 OmniVision CMOS Camera Module OmniVision CMOS Camera Module global Camera Module model CMOS image sensor usb HV7131B EEPROM 93c66 SPCA501
Contextual Info: SPCA501C PC CAMERA CHIPSET GENERAL DESCRIPTION The SPCA501C provides a single chip solution to the PC camera application. It includes all the control, image processing, image compression and data transaction units needed by a PC camera. The compressed data is

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts

NT5DS32M16CS-5T

Abstract: NT5DS64M8CS-5T NT5DS32M16CS nt5ds32m16cs-6k NT5DS64M8CG-5T NT5DS64M8CS-5TI NT5DS128M4CS-5T NT5DS128M4CS-6K DDR400 NT5DS64M8CG
Contextual Info: NT5DS32M16CS NT5DS64M8CS / NT5DS64M8CG NT5DS128M4CS 512Mb DDR SDRAM Feature z DLL aligns DQ and DQS transitions with CK transitions z DDR 512M bit, Die C, based on 90nm design rules z Double data rate architecture: two data transfers per clock cycle

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts

Contextual Info: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency  2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts Units  DQS is edge-aligned with data for reads and is