D9 TO D14 Search Results

U198

Abstract: U5149 u225 U229 diode u1331 u218 MG11A U1401 A1355 U224D
Contextual Info: SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE MISCELLANEOUS HARDWARE & ACCESSORIES SWITCH HARDWARE. D2 - D4 PUSHBUTTON AND TOGGLE CAPS. D5 - D6 SECURITY GUARDS. D7 - D9

Contextual Info: Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Pin Configuration Figures 1.1.3 shows the pin configuration top view . P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5

Contextual Info: Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Pin Configuration Figures 1.1.3 shows the pin configuration top view . P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5

Contextual Info: Renesas microcomputers M16C / 62P Group Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.1.3 to 1.1.5 show the pin configurations top view . P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/AN20/A0(/D0/-)

Contextual Info: Under development This document is under development and its contents are subject to change. M16C/6N Group M16C/6NL, M16C/6NN 1. Overview P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0)

PLQP0100KB-A

Contextual Info: Under development Preliminary specification Specifications in this manual are tentative and subject to change. M32C/8B Group 1. Overview D10 / P1_2 D9 / P1_1 D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3

Contextual Info: Under development This document is under development and its contents are subject to change. M16C/6N Group M16C/6NK, M16C/6NM 1. Overview P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0)

Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to DGG PACKAGE TOP VIEW 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

65LVDS95Q

Abstract: DS90CR215 SN65LVDS95 SN65LVDS95DGGRQ1 SN65LVDS96 SN65LVDS95Q1
Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to DGG PACKAGE TOP VIEW 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 DGG PACKAGE TOP VIEW D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

Contextual Info: M16C/30P Group 1.5 1. Overview Pin Configuration Figures 1.5 to 1.6 show the pin configurations top view . P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15 P2_0/A0 P2_1/A1 P2_2/A2 P2_3/A3 P2_4/A4 P2_5/A5 P2_6/A6 P2_7/A7 VSS

MIL-STD-1553

Abstract: HI-1575PQI
Contextual Info: HI-1575 MIL-STD-1553 3.3V Dual Transceivers with Integrated Encoder / Decoders August 2005 DESCRIPTION 30 29 D5 28 D6 27 D7 26 GND 25 D8 24 D9 23 D10 22 D11 21 - 11 12 13 14 15 16 17 18 19 20 1575PCI 1575PCT AR Y A single write cycle is used to transfer a word to the

DSP56001AFC33

Abstract: DSP56001A DSP56001AFE33 hack br mark
Contextual Info: Pin-out and Package PQFP Top View Package and Tray Descriptions 1 18 Orientation Mark chamfered edge DSP56001AFC33 (Top View) 51 84 nc D20 D19 D18 GNDD GNDD nc D17 D16 nc D15 D14 D13 nc D12 VCCD VCCD D11 nc D10 D9 nc D8 D7 D6 GNDD GNDD nc D5 D4 D3 D2 nc

MOTOROLA TOP MARK

Abstract: L002
Contextual Info: Pin-out and Package PQFP Top View Pin-out and Package Information 18 Orientation Mark chamfered edge (Top View) 51 84 GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDD D13 D12 VCCD D11 D10 GNDD GNDQ VCCQ D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0 DR

P100

Abstract: P101 P102 P103 P104 P105 P106 P107
Contextual Info: Under development Preliminary specification Specifications in this manual are tentative and subject to change. M32C/80 Group 1. Overview 1.5 Pin Assignments P36 / A14 / D14 P37 / A15 ( / D15 ) P40 / A16 P41 / A17 52 51 Vcc2 60 53 P30 / A8 ( / D8 ) 61 P35 / A13 ( / D13 )

lh534y

Abstract: 44-PIN D9 TO D14 A1739
Contextual Info: LH534Y00 CMOS 4M 256K x 16 Mask-Programmable ROM FEATURES • 262,144 words × 16 bit organization PIN CONNECTIONS 40-PIN DIP TOP VIEW • Access time: 120 ns (MAX.) NC 1 40 VCC CE 2 39 A17 D15 3 38 A16 D14 4 37 A15 D13 5 36 A14 • Static operation D12

44-PIN

Abstract: LH532048 QFJ044-P-0650
Contextual Info: LH532048 • Access time: 100 ns MAX. 40-PIN DIP 40-PIN SOP TOP VIEW • Static operation NC 1 40 VCC CE 2 39 NC • TTL compatible I/O D15 3 38 A16 4 • Three-state outputs D14 37 A15 D13 5 36 A14 • Single +5 V power supply D12 6 35 A13 D11 7 34 A12

73D12

Abstract: qfp128 IO769 120 QFP 128p30
Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement PLLVCC PF6/ PF5/ PF4/ PF3/ PF2/ / PF1/ / PF0/ / PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 VSS P81/TxD3 P83/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

50-pin* cf

Abstract: smd a5 gnd a5gnd A09 smd cf card diagram A05 smd A08 smd A08 smd transistor NC7WZ125 smd a10
Contextual Info: 5 4 3 2 1 System Bus Connector 80-pin Receptacle 3.3V CompactFlash Host-Side Socket (50-pin Header, Type II) Access Indicator P1 3.3V D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 C A8 A9 A10 XREG~ WE~ OE~ B R20 0R WAIT~ SWAIT~ R18 0R RDY 3 2 1 INT0~ CS0~ CS1~

SCK D54

Abstract: BGA256 QFP208 SH7750 SH7750R SH7750S HD-36 D2156 VDDRTC
Contextual Info: 1 2 3 4 5 6 7 D33 D45 F D34 D44 G D35 D43 H D36 D42 J D39 D15 D0 D14 D1 D13 D2 D12 D3 D11 D4 D10 D5 D9 M N P R T 14 15 16 VDD-RTC 3.3V VSS-RTC EXTAL2 XTAL2 17 18 19 20 NMI MD1/TXD2 MD0/SCK D63 D48 D62 D49 D61 CA* MD2/RXD2 D50 D60 RD/ / / RXD , , , ,

Contextual Info: 1.2 Block Diagram P47/D7 P46/D6 P45/D5 P44/D4 P43/D3 P42/D2 P41/D1 P40/D0 D15 D14 D13 D12 D11 D10 D9 D8 VCL VCC VCC VSS VSS VSS Figure 1.1 shows an internal block diagram of the HD6413078F20. Data bus MD2 MD1 MD0 EXTAL XTAL RES NMI AS RD HWR Address bus P95/A19/IRQ5

PLQP0100KB-A

Contextual Info: M32C/8A Group 1. Overview A9 / D9 ] [ A10 / D10 [ A11 / D11 [ A12 / D12 [ A13 / D13 [ A14 / D14 [ A15 / D15 A9 , A10 A11 A12 A13 A14 A15 A16 A17 [ , , , , , , A8 , [ A8 / D8 ] ] ] ] ] ] ] D2 D3 D4 D5 D6 D7 / / / / / / A2 A3 A4 A5 A6 A7 [ [ [ [ [ [ , , , ,

PLQP0100KB-A

Contextual Info: M32C/87 Group M32C/87, M32C/87A, M32C/87B ( note 6) A9, [A9/D9] A10, [A10/D10] A11, [A11/D11] A12, [A12/D12] A13, [A13/D13] A14, [A14/D14] A15, [A15/D15] A16 A17 51 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 53 50 49 48 47 46 45 44 43 42 41

PLQP0144KA-A

Abstract: AN15
Contextual Info: M32C/8A Group 1.4 1. Overview Pin Assignments Figures 1.3 and 1.4 show pin assignments top view . A19 A18 A9 , [ A9 / D9 ] A10 , [ A10 / D10 A11 , [ A11 / D11 A12 , [ A12 / D12 A13 , [ A13 / D13 A14 , [ A14 / D14 A15 , [ A15 / D15 A16 A17 73 74 75 76 77 78