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    D1826 Price and Stock

    Amphenol PCD ELFD1826G

    5MM/.197" DUAL ROW OFFSET R/A HD
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    DigiKey ELFD1826G Bulk 100
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    Interstate Connecting Components ELFD1826G
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    Fischer Elektronik GmbH & Co KG SL-16-SMD-182-6-Z

    0.635 MM FOR INTERCONNECTION
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    DigiKey SL-16-SMD-182-6-Z Bulk 10
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    Fischer Elektronik GmbH & Co KG SL-15-SMD-182-6-Z

    0.635 MM FOR INTERCONNECTION
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    DigiKey SL-15-SMD-182-6-Z Bulk 10
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    Fischer Elektronik GmbH & Co KG SL-16-SMD-182-6-S

    0.635 MM FOR INTERCONNECTION
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    DigiKey SL-16-SMD-182-6-S Bulk 10
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    ABLIC Inc. S-1711D1826-M6T1G

    IC REG LIN 1.8V/2.6V 150MA SOT23
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    DigiKey S-1711D1826-M6T1G Reel 3,000
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    Avnet Americas S-1711D1826-M6T1G Reel 3,000
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    Find more D1826 price and stock on Findchips.com

    D1826 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    IS61QDB22M36

    Abstract: D0-35 IS61QDB24M18
    Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered


    Original     		PDF IS61QDB22M36-300M3 IS61QDB22M36-300M3L IS61QDB24M18-300M3 IS61QDB24M18-300M3L IS61QDB22M36-250M3 IS61QDB22M36-250M3L IS61QDB24M18-250M3 IS61QDB24M18-250M3L IS61QDB22M36-200M3L IS61QDB24M18-200M3L IS61QDB22M36 D0-35 IS61QDB24M18

    IS61DDB21M36

    Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
    Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late


    Original     		PDF oDDB22M18-250M3L 1Mx36 2Mx18 IS61DDB21M36 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI

    D0-35

    Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
    Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61QDB42M36-300M3 IS61QDB44M18-300M3 IS61QDB42M36-250M3 IS61QDB44M18-250M3 2Mx36 4Mx18 D0-35 IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3

    IS61QDB41M36

    Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
    Text: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61QDB41M36-250M3 IS61QDB41M36-250M3L IS61QDB41M36-200M3 IS61QDB42M18-200M3 1Mx36 2Mx18 IS61QDB41M36 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 512Kx36 1Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 1Mx18 IS61QDB451236A 15x17x1

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 1Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 4 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available.


    Original     		PDF IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 4Mx18 13x15

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     512Kx36 and 1Mx18 configuration available.


    Original     		PDF IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 512Kx36 1Mx18 13x15

    8502 400 494 811

    Abstract: comcode D-181781 Lucent Technologies fiber lucent comcode b-oversheath lucent LXE 8544B 811 tube D-181683
    Text: fiber.book : sec11.fm Page 12 Thursday, June 22, 2000 11:40 AM Associated Kits for the UCB Closure CSM Kit Central Strength member tie down kit for loose tube cables. Product Code Comcode CSM Kit 107 010 290 Product Code Comcode Racetrack Grommet 845 628 775


    Original     		PDF sec11 25-foot 51D3-LG2 D-182546 31-inch D-182547 41-inch 2492C) 8502 400 494 811 comcode D-181781 Lucent Technologies fiber lucent comcode b-oversheath lucent LXE 8544B 811 tube D-181683

    Untitled

    Abstract: No abstract text available
    Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late


    Original     		PDF IS61DDB21M36-250M3 IS61DDB22M18-250M3 1Mx36 2Mx18

    2SA1413-Z

    Abstract: 2SC3632-Z
    Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid


    Original     		PDF

    2SB1261

    Abstract: No abstract text available
    Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社


    Original     		PDF 2SB1261 1261-Z O-251MP-3 VCEO-60 O-252MP-3Z D18262JJ4V0DS004 D18262JJ4V0DS

    2SC3631

    Abstract: No abstract text available
    Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社


    Original     		PDF 2SC3631 3631-Z Cycle50 O-251MP-3 O-252MP-3Z D18266JJ3V0DS003 TC-5907A D18266JJ3V0DS

    2SB768

    Abstract: 2SD1033
    Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid


    Original     		PDF

    d917

    Abstract: IS61DDB41M36 IS61DDB42M18
    Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 4) CIO Synchronous SRAMs . ISSI May 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61DDB41M36-250M3 IS61DDB42M18-250M3 1Mx36 2Mx18 d917 IS61DDB41M36 IS61DDB42M18

    IS61QDB41M36-200M3

    Abstract: IS61QDB42M18 IS61QDB42M18-200M3 D0-35 IS61QDB41M36 2M x 18
    Text: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . ISSI May 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61QDB41M36-200M3 IS61QDB42M18-200M3 1Mx36 2Mx18 IS61QDB41M36-200M3 IS61QDB42M18 IS61QDB42M18-200M3 D0-35 IS61QDB41M36 2M x 18

    NEC UPD44164182

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44164082, 44164182, 44164362 18M-BIT CMOS SYNCHRONOUS FAST SRAM DOUBLE DATA RATE 2-WORD BURST OPERATION Description The µPD44164082 is a 2,097,152-word by 8-bit, the µPD44164182 is a 1,048,576-word by 18-bit and the µPD44164362


    Original     		PDF PD44164082, 18M-BIT PD44164082 152-word PD44164182 576-word 18-bit PD44164362 288-word 36-bit NEC UPD44164182

    IS61QDB21M18A

    Abstract: No abstract text available
    Text: IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 18Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.


    Original     		PDF IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 1Mx18 wiIS61QDB21M18A-250B4LI

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available. On-chip Delay Locked Loop (DLL) for wide data


    Original     		PDF IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 4Mx18 13x15

    IS61QDB41M18A

    Abstract: No abstract text available
    Text: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid


    Original     		PDF IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 1Mx18 13x15

    IS61QDB22M36A

    Abstract: No abstract text available
    Text: IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid window.


    Original     		PDF IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 2Mx36 4Mx18 13x15 IS61QDB22M36A-333B4I IS61QDB22M36A-333B4LI IS61QDB24M18A-333B4I IS61QDB22M36A

    IS61QDB42M36A

    Abstract: B0821
    Text: IS61QDB44M18A IS61QDB42M36A 4Mx18, 2Mx36 72Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.


    Original     		PDF IS61QDB44M18A IS61QDB42M36A 4Mx18, 2Mx36 2Mx36 4Mx18 IS61QDB42M36A-400B4I IS61QDB42M36A-400B4LI IS61QDB44M18A-400B4I IS61QDB44M18A-400B4LI IS61QDB42M36A B0821