CY7C601A Search Results

CY7C601

Abstract: CY7C601A bicc CY7C602A WORD11
Contextual Info: CY7C601A CYPRESS SEMICONDUCTOR Features • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — Most instructions execute in a single cycle • Very high performance — 25-, 33*, and 40-MHz clock speeds yield 18,24, and 29 MIPS sustained

7C601

Abstract: C32S CY7C325 C3253
Contextual Info: PRELIMINARY £25 CYPRESS SEMICONDUCTOR • Timing Control Unit, Clock Genera­ tor for CY7C601A and CY7C611A SPARC processors • Supports 25-, 33-, 40-MHz operation • Simplifies interface to slow memory and peripherals by eliminating the need for wait-state logic

CY7C601

Abstract: cccv
Contextual Info: CY7C601A r ^ y p p r c c • — 32-Bit RISC Processor SEMICONDUCTOR — R egisters can be u sed a s e ight w in­ dows o f 24 registers each for low pro ced u re overhead Features • Reduced In stru c tio n Set C om puter R ISC A rchitecture — Sim ple fo rm at in stru ctio n s

CY7C157A

Contextual Info: CY7C601A CYPRESS SEMICONDUCTOR 32-Bit RISC Processor — Registers can be used as eight win­ dows of 24 registers each for low procedure overhead — Registers can also be used as regis­ ter banks for fast context switching Features • Reduced Instruction Set Computer

Contextual Info: PRELIM INARY CYPRESS SEMICONDUCTOR • Timing Control Unit, Clock Genera­ tor for CY7C601A and CY7C611A SPARC processors • Supports 25-, 33-, 40-MHz operation • Sim plifies interface to slow memory and peripherals by elim inating the need for wait-state logic

CY7C601

Abstract: CY7C600 7C600 CY7C157A
Contextual Info: • - ^ SEMICONDUCTOR Introduction to RISC and com piler design. A t each step, com puter architects must ask: to what extent does a feature improve o r degrade perform ance and is it w orth the cost of im plem entation? Each additional feature, no m atter how useful it is in an isolated instance, makes all others p er­

Contextual Info: CYPRESS MbE D SEMICONDUCTOR ^ asa-Ttta oao74t.i T - M i- n - 3 8 CYPRESS SEMICONDUCTOR • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance — 25-, 33-, and 40-MHz clock speeds

CY7C601

Contextual Info: " ^ ^ 5 jF CY7C604A _ - _ - . - - - • - Cache Controller and Memory Management Unit CYPRESS — SEMICONDUCTOR Features • Fully conforms to the SPARC Reference Memory M anagement Unit M M U Architecture • Hardware table walk Description

TAG scr Selection Guide

Abstract: CY7C604
Contextual Info: CYPRESS SEMICONDUCTOR 4bE D m asa^bbs 0007475 1 ^ 5 3 - - 3 3 - a .S T CYPRESS SEMICONDUCTOR • Fully conforms to the SPARC Refer­ ence Memory Management Unit MMU Architecture • Support for virtual memory • Supports context snitching — 4096 contexts for TLB entries

Cy7C601

Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af­ ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048

7C602

Abstract: CY7C601
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

NEC B1100

Abstract: b1100 nec UPD65031 PD65031 UPD650 MCA600ECL upd65022 UPD65012 upd65051 UPD65006
Contextual Info: ADVANCED . INTERCONNECTIONS « Device To PGA Socket Cross Reference 5 Energy Way, P.O. Box 1019, West Warwick, Rl 02893 . Tel. 4 0 1 -8 23 -52 0 0 • FAX 401-823-8723 Device To PGA Socket Cross Reference Altera Device # Footprint # EP1800 EPM 5128 EPM5192

Cy7C601

Abstract: CY7C605 c5wg
Contextual Info: 4t.E D CYPRESS SEMICONDUCTOR El H S Ö i L b a 0 0 0 7 4 0 4 S S3 CYP CY7C605A -_-ra ¿rar y — zr^r CYPRESS SEMICONDUCTOR Features Cache Controller and Memory Management Unit Fully conforms to the SPARC refer­ ence M emory M anagement Unit M M U architecture

CY7C601

Contextual Info: CYPRESS SEMICONDUCTOR 4LE » a s a ^ b L S - \2 .- 5 CYPRESS SEMICONDUCTOR Direct interface to CY7C601 integer unit Dircct interface to CY7C157 Caciie Storage Unit CSU Full compliance with ANSI/IEEE-754 standard for binary floating-point arithm etic Supports single and double precision

Cy7C601

Abstract: STD-745-1985 cy7c601a
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • Full compliance with ANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

CY7C157A

Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC processor optimized for em ­ bedded control applications 32-Bit RISC Controller — Privileged instructions • 136 32-bit registers — Eight overlapping windows o f 24 registers each • Artificial intelligence support