CY7C1368C Search Results
CY7C1368C Price and Stock
Rochester Electronics LLC CY7C1368C-166AXCIC SRAM 8MBIT PARALLEL 100TQFP |
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CY7C1368C-166AXC | Tray | 1,543 | 33 |
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Cypress Semiconductor CY7C1368C-166AXCCY7C1368C-166AXC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1368C-166AXC | 88 | 34 |
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CY7C1368C-166AXC | 1,543 | 1 |
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CY7C1368C Datasheets (5)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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CY7C1368C |
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9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | |||
CY7C1368C-166AJXC |
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9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | |||
CY7C1368C-166AXC |
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9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | |||
CY7C1368C-166AXCT |
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Memory, Integrated Circuits (ICs), IC SRAM 8MBIT 166MHZ 100LQFP | Original | |||
CY7C1368C-166AXI |
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9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original |
CY7C1368C Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state |
Original |
CY7C1368C CY7C1368C | |
Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Features Functional Description[1] • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state |
Original |
CY7C1368C CY7C1368C | |
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz CY7C1368C | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz CY7C1368C | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz CY7C1368C | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (Double-Cycle deselect) ❐ Depth expansion without wait state ■ 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz CY7C1368C | |
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz | |
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
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CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz | |
Contextual Info: THIS SPEC IS OBSOLETE Spec No:38-05686 Spec Title:CY7C1368C 9-MBIT 256 K X 32 PIPELINED DCD SYNC SRAM Sunset Owner:Jayasree Nayar (NJY) Replaced by: None CY7C1368C 9-Mbit (256 K x 32) Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM |
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CY7C1368C CY7C1368C 32-bit 250-MHz | |
Contextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz | |
Contextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz | |
FSQ510 Equivalent
Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
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GP-20) FSQ510 Equivalent BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2 | |
CY7C1338-100AXC
Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
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CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC |