CY7C1353 Search Results

4435a

Abstract: CY7C1353G CY7C1353G-133AXC
Contextual Info: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices

CY7C1353G

Abstract: CY7C1353G-100AXC
Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1353F

Abstract: CY7C1353F-100AC CY7C1353F-100AI CY7C1353F-117AC CY7C1353F-117AI CY7C1353F-133AC CY7C1353F-133AI
Contextual Info: CY7C1353F 4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture Features • Burst Capability—linear or interleaved burst order • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

CY7C1353G

Abstract: CY7C1353G-133AXC
Contextual Info: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices

CY7C1353S

Contextual Info: CY7C1353 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 66-M Hz bus operations with zero wait states — Data is transferred on every clock

CY7C1353F

Contextual Info: CY7C1353F PRELIMINARY 256K x 18 Flow-through SRAM with NoBL Architecture Features Functional Description • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate

Contextual Info: CY7C1353F 4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture Features • Burst Capability—linear or interleaved burst order • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

CY7C1353G

Abstract: CY7C1353G-100AXC
Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1350

Abstract: CY7C1351 CY7C1353
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98357 VERSION 1.1 May, 1999 4 Meg SRAM With NoBL Architecture R42D Technology, Hot Aluminum CY7C1350 128K x 36 Pipelined SRAM CY7C1351 128K x 36 Flow-Through SRAM CT7C1352 256K x 18 Pipelined SRAM CY7C1353

CY7C1353B

Abstract: MCM63Z819
Contextual Info: CY7C1353B PRELIMINARY 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 117-MHz bus operations with zero wait states

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1353

Contextual Info: fax id:1104 PRELIMINARY CY7C1353 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Supports 66-MHz bus operations with zero wait states−Data is transferred on every clock The CY7C1353 is a 3.3V 256K by 18 Synchronous-Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped

CY7C1353

Abstract: MCM63Z819
Contextual Info: 353 CY7C1353 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock

Contextual Info: CY7C1353G PRELIMINARY 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

353B

Abstract: CY7C1353B MCM63Z819
Contextual Info: 353B CY7C1353B PRELIMINARY 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 117-MHz bus operations with zero wait states

CY7C1353

Abstract: MCM63Z819 A1413-5
Contextual Info: 1353 CY7C1353 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices MCM63Z819 and MT55L256L18F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock

CY7C1353

Abstract: CY7C1353-66AC MCM63Z819
Contextual Info: / CY7C1353 H Y P R F .S S ^ = 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description Pin c o m p a tib le and fu n c tio n a lly eq u iv alen t to ZB T™ d evic es M C M 6 3Z 81 9 and M T 55L 25 6L 18 F S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w a it sta tes

Contextual Info: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1353

Abstract: MCM63Z819
Contextual Info: CY7C1353 256Kx18 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock