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    CY7C135 Search Results

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    CY7C135 Price and Stock

    Rochester Electronics LLC CY7C1356A-100AC

    IC SRAM 9MBIT PAR 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1356A-100AC Bulk 3,206 48
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    Rochester Electronics LLC CY7C1354S-200BGC

    IC SRAM 9MBIT PARALLEL 119PBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1354S-200BGC Bag 1,338 24
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    Rochester Electronics LLC CY7C135-25JC

    IC SRAM 32KBIT PARALLEL 52PLCC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C135-25JC Bulk 1,043 14
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    Rochester Electronics LLC CY7C1354SV25-166AXC

    IC SRAM 9MBIT PARALLEL 100TQFP
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    DigiKey CY7C1354SV25-166AXC Bag 1,014 25
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    Rochester Electronics LLC CY7C1355C-100BGC

    IC SRAM 9MBIT PAR 119PBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1355C-100BGC Tray 369 28
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    CY7C135 Datasheets (493)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C135 Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Original PDF
    CY7C135 Cypress Semiconductor 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Original PDF
    CY7C1350 Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350 Cypress Semiconductor NoBL, The ZBT-Compatible Family Original PDF
    CY7C1350-100AC Cypress Semiconductor 128K x 36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-100AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-133AC Cypress Semiconductor 128K x 36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-133AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-143AC Cypress Semiconductor 128K x 36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-143AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-80AC Cypress Semiconductor 128K x 36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350-80AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350B Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350B-143AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350B-150AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350B-166AC Cypress Semiconductor 128Kx36 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1350F Cypress Semiconductor 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Original PDF
    CY7C1350F-100AC Cypress Semiconductor 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Original PDF
    CY7C1350F-100AI Cypress Semiconductor Original PDF
    CY7C1350F-100BGC Cypress Semiconductor Original PDF
    ...

    CY7C135 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY7C1350

    Abstract: IDT71V546 MCM63Z736
    Text: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait


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    CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 143-MHz CY7C1350 IDT71V546 MCM63Z736 PDF

    7C1351-40

    Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
    Text: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states


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    CY7C1351 128Kx36 IDT71V547, MT55L128L36F MCM63Z737 66-MHz CY7C1351 7C1351-40 7C1351-50 7C1351-66 IDT71V547 MCM63Z737 PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


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    CY7C1355C, CY7C1357C CY7C1355C/CY7C1357C CY7C1355C PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need


    Original
    CY7C1352G CY7C1352G PDF

    CY7C1352

    Abstract: MCM63Z818 MCM63Z819
    Text: CY7C1352 CY7C1352 256K x18 Pipelined SRAM with NoBL Architecture Features • Low standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states


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    1CY7C1352 CY7C1352 MCM63Z818 MT55L256L18P 143-MHz CY7C1352 MCM63Z819 PDF

    CY7C1352B-100AC

    Abstract: cy7c1352b-166ac CY7C1352B MCM63Z818 MCM63Z819 1352B-2
    Text: PRELIMINARY CY7C1352B 256K x18 Pipelined SRAM with NoBL Architecture • Low standby power Features Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of


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    CY7C1352B CY7C1352B MCM63Z819 MT55L256L18P. CY7C1352B-100AC cy7c1352b-166ac MCM63Z818 1352B-2 PDF

    CY7C1354C

    Abstract: CY7C1356C
    Text: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz


    Original
    CY7C1354C CY7C1356C 36/512K 250-MHz CY7C1354C CY7C1356C PDF

    GVT71256ZC36B-7.5

    Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
    Text: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns


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    CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 GVT71256ZC36B-7.5 CY7C1356A-100AC CY7C1356A GVT71512ZC18 PDF

    CY7C1357A

    Abstract: GVT71512ZB18
    Text: CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns


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    1CY7C1357A CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 CY7C1357A GVT71512ZB18 PDF

    CY7C1350

    Abstract: No abstract text available
    Text: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736


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    CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 CY7C1350 143-MHz PDF

    7C1351-40

    Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737 DQ31-0
    Text: fax id: 1102 Back CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states


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    CY7C1351 128Kx36 IDT71V547, MT55L128L36F MCM63Z737 66-MHz CY7C1351 7C1351-40 7C1351-50 7C1351-66 IDT71V547 MCM63Z737 DQ31-0 PDF

    CY7C1352

    Abstract: MCM63Z818 MCM63Z819
    Text: fax id: 1101 Back CY7C1352 PRELIMINARY 256K x18 Pipelined SRAM with NoBL Architecture Features • Low standby power • Pin compatible and functionally equivalent to ZBT devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states


    Original
    CY7C1352 MCM63Z818 MT55L256L18P 143-MHz CY7C1352 MCM63Z819 PDF

    CY7C1342

    Abstract: CY7C135
    Text: 342 and 4K x 8 Dual-Port Static RAM with Semaphores CY7C135 CY7C1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization


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    CY7C135 CY7C1342 65-micron 7C1342 52-pin IDT7134/IDT71342 CY7C135 CY7C1342 PDF

    EOIZ

    Abstract: No abstract text available
    Text: CY7C1351 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description The CY7C1351 is a 3.3V 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the


    OCR Scan
    CY7C1351 128Kx36 IDT71V547, MT55L128L36F, MCM63Z737 66-MHz EOIZ PDF

    CY7C1352

    Abstract: MCM63Z818 MCM63Z819
    Text: PRELIMINARY CY7C1352 256K x18 Pipelined SRAM with NoBL Architecture • Low standby power Features • Pin compatible and functionally equivalent to ZBT devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states — Data is transferred on every clock


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    CY7C1352 MCM63Z818 MT55L256L18P 143-MHz CY7C1352 MCM63Z819 PDF

    CY7C1352G

    Abstract: CY7C1352G-166AXC CY7C1352G-166AXI CY7C1352G-200AXC CY7C1352G-200AXI CY7C1352G-250AXC CY7C1352G-250AXI
    Text: CY7C1352G PRELIMINARY 4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE


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    CY7C1352G 256Kx18) CY7C1352G CY7C1352G-166AXC CY7C1352G-166AXI CY7C1352G-200AXC CY7C1352G-200AXI CY7C1352G-250AXC CY7C1352G-250AXI PDF

    cy7c1354c-200bgxc

    Abstract: CY7C1354C CY7C1356C M11 68
    Text: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz


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    CY7C1354C CY7C1356C 36/512K 250-MHz CY7C1354C CY7C1356C cy7c1354c-200bgxc M11 68 PDF

    4435a

    Abstract: CY7C1353G CY7C1353G-133AXC
    Text: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices


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    CY7C1353G 133-MHz CY7C1353G 4435a CY7C1353G-133AXC PDF

    7C1354V25-100

    Abstract: CY7C1354 CY7C1354V25 CY7C1356V25 R1538
    Text: 356V25 CY7C1354V25 CY7C1356V25 PRELIMINARY 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ • Supports 200-MHz bus operations with zero wait states — Data is transferred on every clock


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    356V25 CY7C1354V25 CY7C1356V25 256Kx36/512Kx18 200-MHz 166-MHz 133-MHz 7C1354V25-100 CY7C1354 CY7C1354V25 CY7C1356V25 R1538 PDF

    sem 2005

    Abstract: CY7C1342 CY7C135
    Text: CY7C135 CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power


    Original
    CY7C135 CY7C1342 65-micron 7C1342 52-pin CY7C135 CY7C1342 sem 2005 PDF

    CY7C1354C-200BGXC

    Abstract: No abstract text available
    Text: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz


    Original
    CY7C1354C CY7C1356C 36/512K 250-MHz 200-MHz 166-MHz CY7C1354C-200BGXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1354CV25 CY7C1356CV25 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible with and functionally equivalent to ZBT™


    Original
    CY7C1354CV25 CY7C1356CV25 CY7C1354CV25/CY7C1356CV25 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1351G 4-Mbit 128K x 36 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™


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    CY7C1351G 133-MHz 100-Pin 119-Ball PDF

    CY7C1350B-80AC

    Abstract: CY7C1350B
    Text: PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states


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    CY7C1350B 128Kx36 IDT71V546, MT55L128L36P, MCM63Z736 166-MHz 150-MHz 143-MHz 133-MHz CY7C1350B-80AC CY7C1350B PDF