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Infineon Technologies AG CY7C1328G-133AXI IC SRAM 4.5MBIT PAR 100TQFP
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DigiKey	CY7C1328G-133AXI	Tray			144	1 - 10 - 100 - 1000 $5.94007 10000 $5.94007	Buy Now
Infineon Technologies AG CY7C1328G-133AXIT IC SRAM 4.5MBIT PAR 100TQFP
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DigiKey	CY7C1328G-133AXIT	Reel				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1328G-133AXIKJ IC SRAM 4.5MBIT PAR 100TQFP
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DigiKey	CY7C1328G-133AXIKJ	Bulk			58	1 - 10 - 100 $5.2 1000 $5.2 10000 $5.2	Buy Now
Cypress Semiconductor CY7C1328G-133AXIKJ CY7C1328G-133AXIKJ
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Verical	CY7C1328G-133AXIKJ		181		60	1 - 10 - 100 $6.25 1000 $6.25 10000 $6.25	Buy Now
Rochester Electronics	CY7C1328G-133AXIKJ		181		1	1 - 10 - 100 $4.75 1000 $4.25 10000 $4	Buy Now

CY7C1328G Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1328G		Cypress Semiconductor	4-Mbit (256K x 18) Pipelined DCD Sync SRAM		Original	PDF
CY7C1328G-133AXC		Cypress Semiconductor	4-Mbit (256K x 18) Pipelined DCD Sync SRAM		Original	PDF
CY7C1328G-133AXI		Cypress Semiconductor	4-Mbit (256K x 18) Pipelined DCD Sync SRAM		Original	PDF
CY7C1328G-133AXI		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 4.5MBIT 133MHZ 100TQFP		Original	PDF
CY7C1328G-133AXIT		Cypress Semiconductor	4-Mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V		Original	PDF
CY7C1328G-133AXIT		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 4.5MBIT 133MHZ 100TQFP		Original	PDF
CY7C1328G-166AXC		Cypress Semiconductor	4-Mbit (256K x 18) Pipelined DCD Sync SRAM		Original	PDF

CY7C1328G Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1328G-200AXC Abstract: CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture	Original	CY7C1328G 250-MHz 100-Pin 133-MHz CY7C1328G-200AXC CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC	PDF
CY7C1328G Abstract: CY7C1328G-166AXC CY7C1328G-200AXC CY7C1328G-250AXC Contextual Info: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture	Original	CY7C1328G 18-bit 250-MHz CY7C1328G CY7C1328G-166AXC CY7C1328G-200AXC CY7C1328G-250AXC	PDF
Contextual Info: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture	Original	CY7C1328G 18-bit 250-MHz 200-MHz 166-MHz 133-MHz CY7C1328G	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G 133-MHz	PDF
Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture	Original	CY7C1328G 250-MHz 200-MHz 167-MHz 133-MHz 100-pin	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description[1] • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G CY7C1328G	PDF
Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture	Original	CY7C1328G 250-MHz 200-MHz 167-MHz 100-pin	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G 133-MHz	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G 133-MHz	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G CY7C1328G	PDF
Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture	Original	CY7C1328G 250-MHz 100-Pin CY7C1328G 133-MHz	PDF
CY7C1328G Abstract: CY7C1328G-133AXI Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G 250-MHz 100-pin CY7C1328G CY7C1328G-133AXI	PDF
Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state	Original	CY7C1328G CY7C1328G	PDF
Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture	Original	CY7C1328G 250-MHz 100-Pin CY7C1328G 133-MHz	PDF