CY7C1319KV18 Search Results
CY7C1319KV18 Price and Stock
FLIP ELECTRONICS CY7C1319KV18-250BZXCIC SRAM 18MBIT PAR 165FBGA |
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CY7C1319KV18-250BZXC | Tray | 30 |
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Rochester Electronics LLC CY7C1319KV18-250BZXCIC SRAM 18MBIT PAR 165FBGA |
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CY7C1319KV18-250BZXC | Bulk | 14 |
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Infineon Technologies AG CY7C1319KV18-250BZXCIC SRAM 18MBIT PAR 165FBGA |
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CY7C1319KV18-250BZXC | Tray | 680 |
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CY7C1319KV18-250BZXC | Tray | 0 Weeks, 2 Days | 35 |
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Cypress Semiconductor CY7C1319KV18-250BZXCSRAM Chip Sync 1.8V 18M-bit 1M x 18 10ns 165-Pin FBGA Tray |
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CY7C1319KV18-250BZXC | 95 | 25 |
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CY7C1319KV18-250BZXC | 95 | 1 |
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CY7C1319KV18-250BZXC | 1,858 |
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CY7C1319KV18 Datasheets (2)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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CY7C1319KV18-250BZC |
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Integrated Circuits (ICs) - Memory - IC SRAM 18M PARALLEL 165FBGA | Original | |||
CY7C1319KV18-250BZXC |
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Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA | Original |
CY7C1319KV18 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth |
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CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18 | |
Contextual Info: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth |
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CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz | |
Contextual Info: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth |
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CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz | |
Contextual Info: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth |
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CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz | |
Contextual Info: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8 |
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CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1317KV18 CY7C1917KV18 CY7C1319KV18 | |
Contextual Info: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18 Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8 |
Original |
CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1317KV18 CY7C1917KV18 CY7C1319KV18 | |
Contextual Info: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency |
Original |
CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit 333-MHz | |
M30-15Contextual Info: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth |
Original |
CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz M30-15 |