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    CQ 1265

    Abstract: 3M Touch Systems
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original
    36-Mbit CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 CY7C1261KV18 CY7C1276KV18 CY7C1263KV18 CQ 1265 3M Touch Systems PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original
    CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit CY7C1263KV18 PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original
    36-Mbit CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 CY7C1261KV18 CY7C1276KV18 CY7C1263KV18 3M Touch Systems PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1263KV18, CY7C1265KV18 36-Mbit CY7C1263KV18 3M Touch Systems PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1263KV18/CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1263KV18/CY7C1265KV18 36-Mbit CY7C1265KV18 PDF