CY7B Search Results

SMPTE-125M

Abstract: nrzi encoder 8b/10b scrambler CY7B9234 CY7C9235 259M-BCD
Contextual Info: PRELIMINARY CY7C9235 SMPTE-259M/DVB-ASI Scrambler-Controller Features a CY7B9234 HOTLink transmitter, which then converts the bit-parallel characters into a SMPTE-259M compatible high-speed serial data stream. • Fully compatible with SMPTE-259M-BCD — SMPTE-125M compliant for 4:2:2 component video

b9236

Abstract: B9233 CY7B923-jC CY7B933 CY7B923 foto sensor B9237 7B923
Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • • that transfer data over high-speed serial links fiber, coax, and twisted pair . Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also available for high speed applications (160-400 Mbits/second), as

CY7B9911V

Abstract: 7B9911V-8
Contextual Info: CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB Features selectable control over system clock functions. These multipleoutput clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance

CY78991

Abstract: CY7B991 CY7B9911 CY7B9911V CY7B9911V-5JC
Contextual Info: CY7B9911V 3.3V RoboClock+ m CYPRESS High Speed Low Voltage Programmable Skew Clock Buffer PRELIMINARY Features • All output pair skew <100 ps typical 250 max. • 3 .7 5 -to 110-MHz output operation • User-selectable output functions — Selectable skew to 18 ns

1001dl

Abstract: IR Sensor transmitter and receiver pair datasheet qsc 1110 receiver CONTROLLER rx-2 CY7B9234 CY7B9334 CY7C9235 CY7C9335
Contextual Info: CY7B9234 CY7B9334 PRELIMINARY SMPTE HOTLink Transmitter/Receiver Features SMPTE-259M-BCD compliant along with SMPTE-259M encoder CY7C9235 and decoder (CY7C9335) Fibre Channel compliant DVB-ASI compliant RX PLL tolerant of long run length data patterns (>20

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B991V

Abstract: R2130
Contextual Info: fax id: 3550 CY7B991V 3.3V RoboClock W OYPHESS Low Voltage Programmable Skew Clock Buffer PRELIMINARY Features functions. T hese m ultiple-output clo ck drivers provide the sys­ tem integrator w ith fun ctions ne cessa ry to optim ize the tim ing o f h igh -perform a nce co m p u te r system s. Eight individual d riv ­

Contextual Info: CY7B9911V 3.3 V RoboClock+ , High Speed Low Voltage Programmable Skew Clock Buffer 3.3 V RoboClock+™, High Speed Low Voltage Programmable Skew Clock Buffer Features • All output pair skew <100 ps typical 250 max ■ 3.75 to 110 MHz output operation

CY7B991V

Contextual Info: CY7B991V 3.3V RoboClock Low Voltage Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

A120

Abstract: CY7B9532-AC CY7B9532-AI CY7B9532V
Contextual Info: PRELIMINARY CY7B9532V SONET OC-48 Transceiver Features • • • • • • • • • SONET OC-48 operation Full Bellcore and ITU jitter compliance 2.488-GBaud serial signaling rate Multiple selectable loopback/loop-through modes Single 155.52-MHz reference clock

Contextual Info: fax id: 3550 CY7B991V 3.3V RoboClock PRELIMINARY Low Voltage Programmable Skew Clock Buffer Features • All output pair skew <100 ps typical 250 max. • 3.75- to 80-M Hz output operation • User-selectable output functions — Selectable skew to 18 ns

Contextual Info: CY7B194 CY7B195 CY7B196 PRELIMINARY CYPRESS SEMICONDUCTOR 65,536 x 4 Static R/W RAM Features Functional Description • High speed — tAA = 10 ns • BiCMOS for optimum speed/power • Low active power — 825 mW • Low standby power — 330 mW • Automatic power-down when

Contextual Info: CY7B8392 CYPRESS Ethernet Coax Transceiver Interface Features Functional Description • • • • • Compliant with IEEE802.310BASE5 and 10BASE2 Pin compatible with the popular 8392 Internal squelch circuit to eliminate input noise Hybrid mode collision detect for extended distance

Contextual Info: CY7B161 CY7B162 f ' YPPI7QC! SEMICONDUCTOR Features Functional Description • U ltra high speed — 8 ns tAA • Low active power — 700 mW • Low standby power — 250 mW • Transparent write (7B161 • BiCMOS for optimum speed/power • TTL-compatible inputs and outputs

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 •■mmmmggf ¿mw Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

Contextual Info: PRELIMINARY SEMCONDUCTOR CY7B138 CY7B139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • 0.8-micron BiCMOS for high per­ formance • High-speed access — 15 ns com’l — 25 ns (mil) • Automatic power-down • Fully asynchronous operation

Contextual Info: fax id: 3547 W CYPRESS CY7B9911 RoboClock+ ADVANCED INFORMATION High Speed Programmable Skew Clock Buffer PSCB Features All output pair skew <100 ps typical (250 max.) 3.75- to 100-MHz output operation User-selectable output functions — Selectable skew to 18 ns

Contextual Info: CY7B134 CY7B135 CY7B1342 F# CYPRESS 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features Functional D escription • 0.8-micron BiCMOS for high performance T he CY7B134, CY7B135, and CY7B1342 are high-speed BiCMOS 4K x 8 dual-port

Contextual Info: CY7B180 CY7B181 PRELIMINARY CYPRESS SEMICONDUCTOR Features 4K x 18 Cache Tag • Can be used as 4K x 18 SRAM Functional Description Supports 50-MHz cache for all major high-speed processors 4K x 18 tag organization BiCMOS for optimum speed/power High speed

Contextual Info: CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • Output pair skew < 100 ps typical (250 max.) • All outputs skew <250 ps typical (500 max.) • 3.75- to 80-MHz output operation • User-selectable output functions

Contextual Info: CY7B131 CY7B141 F# CYPRESS IK x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron BiCMOS for high perform ance • Automatic power-down • M aster CY7B131 easily expands data bus width to 16 or more bits using slave CY7B141 • BÜ5Ÿ output flag on CY7B131; BUSŸ

Contextual Info: fax id: 5209 ZZZZSESEEEE2 ¿Em rs z g g g p p r ,r T ~ ^ T ~ i T ? o L > I 1 CY7B131 0Y7B141 o - 11 C O D 1 Kx8 Dual-Port Static RAM can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the

Contextual Info: fax id: 5004 CY7B923 CY7B933 H O TLink T ra n sm itte r/R e ce ive d Features • • • • • • • • • • • • • • • • • twisted pair at data rates from 160 to 330 Mbits/second 400 Mbits/second for -400 devices). Figure 1 illustrates typical