CY62147DV18 Search Results

Contextual Info: CY62147DV18 MoBL2 PRELIMINARY 4 Mb 256K x 16 Static RAM Features • • • • • • • • • mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable

Contextual Info: CY62147EV18 MoBL 4-Mbit 256K x 16 Static RAM Features Functional Description • Very high speed: 55 ns ■ Wide voltage range: 1.65 V to 2.25 V ■ Pin compatible with CY62147DV18 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A

CY62147CV18

Abstract: CY62147DV18
Contextual Info: CY62147DV18 MoBL2 4-Mb 256K x 16 Static RAM Features • • • • • • • • • mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable

AN1064

Abstract: CY62147EV18 CY62147EV18LL CY62147DV18
Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Features • Very high speed: 55 ns ■ Wide voltage range: 1.65V–2.25V ■ Pin compatible with CY62147DV18 ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 7 µA

AN1064

Abstract: CY62147DV18 CY62147EV18 CY62147EV18LL
Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Features • Very high speed: 55 ns ■ Wide voltage range: 1.65V–2.25V ■ Pin compatible with CY62147DV18 ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 7 µA

CY62147CV18

Abstract: CY62147DV18
Contextual Info: CY62147DV18 MoBL2 4-Mb 256K x 16 Static RAM Features • • • • • • • • • mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable

Contextual Info: CY62147EV18 MoBL 4-Mbit 256 K x 16 Static RAM 4-Mbit (256 K × 16) Static RAM Features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an

Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM is ideal for providing More Battery Life™ (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the

AN1064

Abstract: CY62147DV18 CY62147EV18 CY62147EV18LL
Contextual Info: CY62147EV18 MoBL 4-Mbit 256K x 16 Static RAM is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the

Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Features consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: • Very high speed: 55 ns

Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Features also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH

Contextual Info: CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Features The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

6T SRAM

Abstract: SRAM 6T 16MB SRAM CY62147DV18 K6F1616R6C MT45W1MW16PD TSOP sensor project micron memory sram
Contextual Info: TN-45-17: CellularRAM Replacing Single- and Dual-CE# SRAM Introduction Technical Note Using CellularRAM Memory to Replace Single- and Dual-Chip Select SRAM Introduction Micron CellularRAM™ devices are designed to be backward-compatible with 6T SRAM

transistor SMD wl3

Abstract: making code WL3 Micron 32MB NOR FLASH making WL3 PSRAM A191 A192 CY62147DV18 K6F1616R6C SRAM 4T cell
Contextual Info: TN-45-30: PSRAM 101 Introduction Technical Note PSRAM 101: An Introduction to Micron CellularRAM® and PSRAM Introduction The mobile phone market has become increasingly cost competitive, demanding interface innovations to support the low-cost requirements inherent in this market. Micron®

CY62147DV18

Abstract: CY62147EV18 CY62147EV18LL
Contextual Info: CY62147EV18 MoBL 4-Mbit 256K x 16 Static RAM Features Functional Description • Very high speed: 55 ns The CY62147EV18 is a high performance CMOS static RAM organized as 256 K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This