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    CRC-32 ETHERNET Search Results

    CRC-32 ETHERNET Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SF-NDCCGF28GB-000.5M Amphenol Cables on Demand Amphenol SF-NDCCGF28GB-000.5M 0.5m SFP28 Cable - Amphenol 25-Gigabit Ethernet SFP28 Direct Attach Copper Cable (1.6 ft) Datasheet
    SF-NDCCGF28GB-001M Amphenol Cables on Demand Amphenol SF-NDCCGF28GB-001M 1m SFP28 Cable - Amphenol 25-Gigabit Ethernet SFP28 Direct Attach Copper Cable (3.3 ft) Datasheet
    SF-NDCCGF28GB-002M Amphenol Cables on Demand Amphenol SF-NDCCGF28GB-002M 2m SFP28 Cable - Amphenol 25-Gigabit Ethernet SFP28 Direct Attach Copper Cable (6.6 ft) Datasheet
    SF-NDCCGF28GB-003M Amphenol Cables on Demand Amphenol SF-NDCCGF28GB-003M 3m SFP28 Cable - Amphenol 25-Gigabit Ethernet SFP28 Direct Attach Copper Cable (9.8 ft) Datasheet
    SF-100GLB0W00-3DB Amphenol Cables on Demand Amphenol SF-100GLB0W00-3DB QSFP 100G Loopback Adapter Module for QSFP28 Port Testing - 3dB Attenuation & 0W Power Consumption [100-Gigabit Ethernet Ready] Datasheet

    CRC-32 ETHERNET Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    MPC5676R

    Abstract: No abstract text available
    Text: Freescale Semiconductor Mask Set Errata MPC5676R_3N23A Rev. 25 JAN 2013 Mask Set Errata for Mask 3N23A Introduction This report applies to mask 3N23A for these products: • MPC5676R Errata ID Errata Title 5037 CRC: CRC-32 Ethernet and CRC-16 (CCITT) operation do not match industry standards.


    Original     		MPC5676R 3N23A 3N23A MPC5676R CRC-32 CRC-16 PDF

    RM0091

    Abstract: No abstract text available
    Text: STM32F048xx ARM -based 32-bit MCU, 32 KB Flash, crystal-less USB FS 2.0, 8 timers, ADC & comm. interfaces, 1.8 V Datasheet - preliminary data Features • Core: ARM 32-bit Cortex-M0 CPU, frequency up to 48 MHz  CRC calculation unit  Power management


    Original     		STM32F048xx 32-bit DocID026007 RM0091 PDF

    MII PHY verilog code for phy interface

    Abstract: c code for ethernet mac verilog code of 32 bit mac RTL code for ethernet verilog code power management verilog code for 100 mbps ethernet ETHERNET-MAC verilog code for switch verilog code for 100mbps ethernet rMII verilog
    Text: Ethernet MAC with 10- and 100-Mbps Operation Highlights ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ E th ern et M A C 32 CSR Address Check Station M anagem ent VCI Rx CRC 32 8 Rx M edia A ccess C ontroller Rx PHY Interface PHY ♦ Optimized for switching, routing, network


    Original     		100-Mbps MII PHY verilog code for phy interface c code for ethernet mac verilog code of 32 bit mac RTL code for ethernet verilog code power management verilog code for 100 mbps ethernet ETHERNET-MAC verilog code for switch verilog code for 100mbps ethernet rMII verilog PDF

    Untitled

    Abstract: No abstract text available
    Text: LAN89730 High-Speed Inter-Chip HSIC USB 2.0 to 10/100 Ethernet Controller for Automotive Applications PRODUCT FEATURES Datasheet Highlights       — — — — — Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal


    Original     		LAN89730 32-bit 48-bit st60-4-227-8870 PDF

    obd II schematics

    Abstract: No abstract text available
    Text: LAN89730 High-Speed Inter-Chip HSIC USB 2.0 to 10/100 Ethernet Controller for Automotive Applications PRODUCT FEATURES Datasheet Highlights       — — — — — Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal


    Original     		LAN89730 32-bit 48-bit st60-4-227-8870 obd II schematics PDF

    SEEQ 8001

    Abstract: JI 3009-2 SEEQ EDLC 8001-t data sheet IC 7432 IC 7217 Unit COUNTER IC TTL 7432 7432 encoder 8253 programme able interface ic 7432 encoder
    Text: 8001 EDLC ETHERNET DATA LINK CONTROLLER PRELIMINARY DATA SHEET DECEMBER 1982 Features Description • 100% Ethernet Compatible ■ 10 MHz Serial/Parallel Conversion ■ Preamble Generation and Removal ■ Automatic 32-Bit FCS CRC Generation and The SEEQ E thernet Data L in k C o n tro lle r (E D L C ) is


    OCR Scan     		32-Bit 200060/30K/1182 SEEQ 8001 JI 3009-2 SEEQ EDLC 8001-t data sheet IC 7432 IC 7217 Unit COUNTER IC TTL 7432 7432 encoder 8253 programme able interface ic 7432 encoder PDF

    hecs 50

    Abstract: MC68EN360 CRC-32 MC68360 PC11 HEAD15 CRC32 "cell search"
    Text: ATOM1 : MC68360 ATM Microcode User’s Manual Document Reference: Version Comments Release date 0.1 First Release 18th Aug., 1994 0.2 Updated User’s Manual 1st Nov., 1994 1.0 Updated for CRC-32 and buffer scattering 21st. March, 1996 Motorola reserves the right to make changes without further notice to any product herein to improve reliability, function,


    Original     		MC68360 CRC-32 0x8000 0x4000) 0x1000) 0x2000) hecs 50 MC68EN360 PC11 HEAD15 CRC32 "cell search" PDF

    0x04c11db7

    Abstract: CRC32POLY 0xEDB88320 0x990951BA 0x77073096 0xe963a535 4F10 AN2745 CRC32 CRC32C
    Text: Freescale Semiconductor Application Note AN2745 Rev. 0, 07/2004 Setting Up TSEC Hash Tables by Dana Castillo NCSD Applications Freescale Semiconductor, Inc. Austin, TX This application note describes the procedure to setup the hash tables for the three-speed Ethernet controller TSEC .


    Original     		AN2745 0x04c11db7 CRC32POLY 0xEDB88320 0x990951BA 0x77073096 0xe963a535 4F10 AN2745 CRC32 CRC32C PDF

    MPC68360

    Abstract: hdlc DSP56300 MCF5206E MCF5272 MPC860 MCF5272UM
    Text: Technical Data MCF 5272HDLCUG Rev. 0, 2/2002 MCF5272 Soft HDLC User’s Guide High Level Data Link Control HDLC is a bit-oriented Open Systems Interconnection (OSI) Layer 2 protocol commonly used in data communications systems. Many other common layer 2 protocols, for example, ISDN LAP-B, ISDN LAP-D, and Ethernet, are heavily based on


    Original     		5272HDLCUG MCF5272 MPC68360 hdlc DSP56300 MCF5206E MPC860 MCF5272UM PDF

    x23 umi

    Abstract: x22 umi fpga vhdl code for crc-32 umi x22 H440 CRC32 CRC-32 P802 k4107 0180C2000001
    Text: ispLever CORE TM LatticeSCM Ethernet flexiMAC MACO Core User’s Guide September 2009 ipug48_01.8 LatticeSCM Ethernet flexiMAC MACO Core User’s Guide Lattice Semiconductor Introduction The LatticeSCM Ethernet flexiMAC™ MACO™ IP core assists the FPGA designer’s efforts by providing pretested, reusable functions that can be easily plugged in, freeing designers to focus on their unique system architecture. These blocks eliminate the need to “re-invent the wheel,” by providing either an industry-standard Layer 2 flexible packet framer and parser or a Layer 1 multi-protocol functionality of the Physical Coding Sublayer PCS


    Original     		ipug48 x23 umi x22 umi fpga vhdl code for crc-32 umi x22 H440 CRC32 CRC-32 P802 k4107 0180C2000001 PDF

    4 bit microprocessor

    Abstract: 32 bit modulo adder parity and crc bit adder
    Text: Implementing Cyclical Redundancy Check with Vantis Devices Application Note Implementing Cyclical Redundancy Check with Vantis Devices INTRODUCTION Reliable communications are a necessity in today’s age, whether between two microprocessors or across an ethernet connection. To ensure reliable communications, it is necessary to check


    Original     		PDF

    GT-48002A

    Abstract: GT-48002 ICS1890 QS6612
    Text: TECHNICAL BULLETIN Galileo Technology TM Differences Between the GT-48002 and GT-48002A November 30, 1996 Rev 1.1 TB-48002A-002 About the GT-48002A The GT-48002A is a feature enhanced version of the original GT-48002 2 Port Fast Ethernet Switch Controller. All of


    Original     		GT-48002 GT-48002A TB-48002A-002 GT-48002A GT-48002, ICS1890 QS6612 PDF

    GT-48001A

    Abstract: No abstract text available
    Text: TECHNICAL BULLETIN Galileo Technology Differences Between the GT-48001 and GT-48001A TM October 23, 1996 Rev 1.1 TB-48001A-002 About the GT-48001A The GT-48001A is a feature enhanced version of the original GT-48001 8 Port Switched Ethernet Controller. All of the


    Original     		GT-48001 GT-48001A TB-48001A-002 GT-48001A GT48001A. GT-48001, PDF

    h946

    Abstract: H945 H944 h965 H924 h940 295050 transistor h945 H948 transistor BC rx
    Text: LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1219 Introduction This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer up to


    Original     		TN1219 10-Gigabit 88X2040 h946 H945 H944 h965 H924 h940 295050 transistor h945 H948 transistor BC rx PDF

    router board 433 circuit diagram for ethernet

    Abstract: fastpath router ixp1240 microengine CRC-32 IXP1200 IXP1250
    Text: IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note - Rev 1.0, 3/20/2002 Order Number: 278393-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual


    Original     		IXP1200 OC-3/12/Ethernet RFC1577 IXP1240 router board 433 circuit diagram for ethernet fastpath router microengine CRC-32 IXP1250 PDF

    traffic light controls using 8086

    Abstract: traffic light 8086 ic laf 0001 Supply Control LAF 0001 10BASE Z8000 microprocessor closed loop control dali s1.2 am7990 laf 0001 power
    Text: Am7990 Advanced Micro Devices Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Compatible with Ethernet and IEEE 802.3 10BASE 5 Type A, and 10BASE 2 Type B, “Cheapernet” • Network and packet error reporting ■ Back-to-back packet reception with as little as


    OCR Scan     		Am7990 10BASE 80x86 680x0, Am29000 Z8000â 24-bit 48-pin traffic light controls using 8086 traffic light 8086 ic laf 0001 Supply Control LAF 0001 Z8000 microprocessor closed loop control dali s1.2 laf 0001 power PDF

    am7990

    Abstract: No abstract text available
    Text: Am7990 Advanced Micro Devices Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Compatible with Ethernet and IEEE 802.3 10BASE 5 Type A, and 10BASE 2 Type B, “Cheapernet” • Network and packet error reporting ■ Back-to-back packet reception with as little as


    OCR Scan     		Am7990 10BASE 80x86 680x0, Am29000 Z8000â 24-bit Am7990 BV8PL028 PDF

    16X10

    Abstract: S5N8946
    Text: S5N8946 ADSL/CABLE MODEM MCU 7 ETHERNET CONTROLLER ETHERNET CONTROLLER OVERVIEW The S5N8946 has an Ethernet controller which operates at either 10-Mbits per second in half-duplex or full-duplex mode. In half-duplex mode, the controller supports the IEEE 802.3 carrier sense multiple access with collision


    Original     		S5N8946 10-Mbits 16X10 PDF

    GMAC

    Abstract: fiber optics cable 12/98 GMII 98YL-0226C Audio transmitting and receiving by Using Fiber Gigabit Ethernet PHY Gigabit Logic
    Text: GIGABIT ETHERNET MEDIA ACCESS CONTROLLER ASIC CORE The Gigabit Ethernet Media Access Controller GMAC ASIC core is a macro designed to increase the network’s bandwidth between routers, switches, hubs, and servers and is expected to be deployed in desktop systems in the near future.


    Original     		8b/10b A14028EU1V0PB00 GMAC fiber optics cable 12/98 GMII 98YL-0226C Audio transmitting and receiving by Using Fiber Gigabit Ethernet PHY Gigabit Logic PDF

    h945

    Abstract: H944 transistor h945 h965 h946 H948 IR1518 BCM56800 h945 transistor H808
    Text: LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1218 Introduction This technical note describes a Physical/MAC layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Broadcom BCM56800 network switch. The test exercises the Physical/MAC layer


    Original     		TN1218 10-Gigabit BCM56800 h945 H944 transistor h945 h965 h946 H948 IR1518 h945 transistor H808 PDF

    Untitled

    Abstract: No abstract text available
    Text: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design AN-647-1.2 Application Note This application note describes Single-Port Triple-Speed Ethernet and On-Board PHY Chip reference designs that demonstrate Ethernet operations of the Altera


    Original     		AN-647-1 88E1111 PDF

    application notes pressure sensor signal conditioner

    Abstract: cml T9 LED ee series ferrite transformer SH Series wakeup KSZ8841 KSZ8841-16MQL KSZ8841-32MQL KSZ8841P
    Text: KSZ8841-16/32 MQL/MVL/MVLI Single-Port Ethernet MAC Controller with Non-PCI Interface Data Sheet Rev 1.3 General Description Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption.


    Original     		KSZ8841-16/32 KSZ8841M KSZ8841-series 8/16-bit 32-bit KSZ8841Mer. application notes pressure sensor signal conditioner cml T9 LED ee series ferrite transformer SH Series wakeup KSZ8841 KSZ8841-16MQL KSZ8841-32MQL KSZ8841P PDF

    T7474

    Abstract: 84302 TXRDY14 seeq84302
    Text: 84302 84302 4-Port Quad 100/10 Mbps Fast Ethernet Controller HURRICANE Ethernet Controller with RMON/SNMP Management Counters Full Duplex TM Technology Incorporated October 29, 1997 ADVANCED DATA SHEET FEATURES Note: Check for latest Data Sheet revision before starting any designs.


    Original     		84C300 MD400171/­ QQ84302 T7474 84302 TXRDY14 seeq84302 PDF

    laf 0001

    Abstract: laf 0001 power AMD 386DX laf 0001 equal "Attachment Unit Interface" lsi 1db6 isa-hub RG58A/U 386DX Z8000
    Text: PRELIMINARY Am79C90 CMOS Local Area Network Controller for Ethernet C-LANCE DISTINCTIVE CHARACTERISTICS • Compatible with Ethernet and IEEE 802.3 10BASE-5 Type A, and 10BASE-2 Type B, “Cheapernet,” 10BASE-T ■ Easily interfaced with 80x86, 680x0, Am29000,


    Original     		Am79C90 10BASE-5 10BASE-2 10BASE-T 80x86, 680x0, Am29000 Z8000TM 64-byte 48-byte laf 0001 laf 0001 power AMD 386DX laf 0001 equal "Attachment Unit Interface" lsi 1db6 isa-hub RG58A/U 386DX Z8000 PDF