CONFIGURATION BEL 187 TRANSISTOR Search Results

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LF9203

Abstract: TG1G L80600 Delta MP 130M Broadcom 4313 9010 FISHER LNK205 E1110 H5007 driver 3h1 ferrite material
Contextual Info: TECHNICAL MANUAL L80600 10/100/1000 Mbits/s Ethernet PHY March 2001 R14022 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

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Contextual Info: Cologne Chip HFC - S mini ISDN HDLC FIFO controller with S/T interface and integrated FIFOs Data Sheet March 2006 Cologne Chip HFC-S mini Revision History Date Remarks March 2006 The consolidation begun with the previous data sheet revision attains its conclusion with this

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Contextual Info: Cologne Chip HFC - S mini ISDN HDLC FIFO controller with S/T interface and integrated FIFOs Data Sheet March 2006 Cologne Chip HFC-S mini Revision History Date Remarks March 2006 The consolidation begun with the previous data sheet revision attains its conclusion with this

LF9203

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Contextual Info: Oct 2009 DP83861VQM-3 EN Gig PHYTER 10/100/1000 Ethernet Physical Layer General Description Features The DP83861 is a full featured Physical Layer transceiver • 100BASE-TX and 1000BASE-T compliant with in tegrated PMD sublayers to su pport 1 0BASE-T, ■ Fully compliant to IEEE 802.3u 100BASE-TX and IEEE

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Contextual Info: DP83861 DP83861 EN Gig PHYTER 10/100/1000 Ethernet Physical Layer Literature Number: SNLS069D Oct 2009 DP83861VQM-3 EN Gig PHYTER 10/100/1000 Ethernet Physical Layer General Description Features bs ol et e The DP83861 is a full featured Physical Layer transceiver • 100BASE-TX and 1000BASE-T compliant

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Contextual Info: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Printed exclusively for DataRace Bt8230 ATM Segmentation and Reassembly Controller—SRC

LF9203

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Contextual Info: April 2001 DP83861VQM-3 EN Gig PHYTER 10/100/1000 Ethernet Physical Layer General Description Features The DP83861 is a full featured Physical Layer transceiver • 100BASE-TX and 1000BASE-T compliant with integrated PMD sublayers to support 10BASE-T, ■ Fully compliant to IEEE 802.3u 100BASE-TX and IEEE

X9265

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BT8230EPFC

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Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S Bt8230 ATM Segmentation and Reassembly Controller-SAR data sheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS Because Communication Matters Bt8230 ATM Segmentation and Reassembly Controller—SAR

Contextual Info: Cologne Chip HFC - E1 ISDN HDLC FIFO controller with Primary Rate Interface E1 Data Sheet October 2007 Cologne Chip Revision History of HFC-E1 Data Sheet Date Remarks October 2007 Minor changes were made in this data sheet revision: Information added to Section 2.2.4

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Contextual Info: Cologne Chip HFC - E1 ISDN HDLC FIFO controller with Primary Rate Interface E1 Data Sheet October 2007 Cologne Chip Revision History of HFC-E1 Data Sheet Date Remarks October 2007 Minor changes were made in this data sheet revision: Information added to Section 2.2.4

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Contextual Info: Cologne Chip HFC - 4S / HFC - 8S ISDN HDLC FIFO controller with 4 / 8 integrated S/T interfaces Data Sheet October 2007 Cologne Chip Revision History of HFC-4S / 8S Data Sheet Date Remarks October 2007 Minor changes were made in this data sheet revision: Information added to Section 2.2.4

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Contextual Info: Cologne Chip HFC - 4S / HFC - 8S ISDN HDLC FIFO controller with 4 / 8 integrated S/T interfaces Data Sheet October 2007 Cologne Chip Revision History of HFC-4S / 8S Data Sheet Date Remarks October 2007 Minor changes were made in this data sheet revision: Information added to Section 2.2.4

Contextual Info: |p I 1.0 Product Description The Bt8230 Segmentation and Reassembly Controller SRC incorporates a host interface, Asynchronous Transfer Mode (ATM) Adaptation Layer processing, and line interfaces in a single device. This highly integrated ATM device combines

Contextual Info: CHAPTER 5 1 Digital I/O PERI PHERAL Ports The uPD75238 contains T he uPD75238 empl oy s I/O ports All data the ports 8-bit enabled Fig. 5- 1 are m app ed memory I/O of and as HARDWARE FUNCTIONS the to data uPD75238, bit I/O ports, port I / O. This m ea ns

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Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

PANASONIC MID INVERTER M1D0

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ss100 transistor

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RC288DPI

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Contextual Info: RC288DPÌ and RC288DPL RC288DPÌ and RC288DPL V.34 Data/V.17 Fax/Voice Modem Data Pumps Rockwell INTRODUCTION FEATURES The Rockwell RC288DPi and RC288DPL are V.34 modem data pump families that support data rates up to 28800 bps, fax operation up to 14400 bps, and voice

Contextual Info: KS8852HLE Two-Port 10/100 Mb/s Ethernet Switch with 8 or 16-Bit Host Interface Revision 1.0 General Description The KSZ8852 product line consists of industrial capable Ethernet switches, providing integrated communication for a range of Industrial Ethernet and general Ethernet

TRANSFORMER 86A-4222A

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Contextual Info: PIC18F23K20/24K20/25K20/26K20/ 43K20/44K20/45K20/46K20 Data Sheet 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology  2010 Microchip Technology Inc. DS41303G Note the following details of the code protection feature on Microchip devices: •