CLOCK 1.8V OSC Search Results

application notes of TF 513

Abstract: PHSOSCK17 PHSOSCK27 STD130
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

CL 2181

Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

A1930

Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

Lpddr2 Idd7

Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

Lpddr2 Idd7

Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2
Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

NTC 200-9

Abstract: a2240 128M16 A1930 NT6SM16M32
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

QFN32

Contextual Info: NB7V586M 1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB7V586M is a differential 1−to−6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an

Contextual Info: NB7V586M 1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB7V586M is a differential 1−to−6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an

48-PIN

Abstract: CDCL6010 CDCL6010RGZR CDCL6010RGZT
Contextual Info: CDCL6010 www.ti.com SLLS780A – FEBRUARY 2007 – REVISED MARCH 2008 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer • FEATURES 1 • Single 1.8V Supply • High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs

48-PIN

Abstract: CDCL6010 CDCL6010RGZR CDCL6010RGZT
Contextual Info: CDCL6010 www.ti.com SLLS780A – FEBRUARY 2007 – REVISED MARCH 2008 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer • FEATURES 1 • Single 1.8V Supply • High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs

Contextual Info: CDCL6010 www.ti.com SLLS780A – FEBRUARY 2007 – REVISED MARCH 2008 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer • FEATURES 1 • Single 1.8V Supply • High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs

48-PIN

Abstract: CDCL6010 CDCL6010RGZR CDCL6010RGZT
Contextual Info: CDCL6010 www.ti.com SLLS780A – FEBRUARY 2007 – REVISED MARCH 2008 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer • FEATURES 1 • Single 1.8V Supply • High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs

NT6SM16M16AG-S1

Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64
Contextual Info: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle

Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

48-PIN

Abstract: CDCL6010 CDCL6010RGZR CDCL6010RGZT
Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

Contextual Info: CDCL6010 www.ti.com SLLS780 – FEBRUARY 2007 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer FEATURES • • • • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11

Oscillators

Abstract: Oscillator ecs 4 pin 40 MHz crystal oscillator
Contextual Info: ECS-1618 RoHS Compliant MSL 1 Lead Finish Au SMD CLOCK OSCILLATOR ECS-1618 +1.8V subminiature SMD oscillators. Ideal for today's high density applications. OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS PARAMETERS ECS-1618 (+1.8V) CONDITIONS MIN Frequency Range

M8000

Abstract: LF24A M4000 JESD22-A114E MO-220
Contextual Info: MoBL Clock M4000/M8000 Four-PLL Programmable Clock Generator for Portable Applications Features Benefits • Device Operating Voltage Options: ❐ MoBL Clock M4000 Family: 1.8V ❐ MoBL Clock M8000 Family: 2.5V, 3.0V, or 3.3V ■ Selectable clock output voltages for both MoBL Clock M4000

M3000

Abstract: LF24A M6000 MO-220
Contextual Info: MoBL Clock M3000/M6000 Three-PLL Programmable Clock Generator for Portable Applications Features Benefits • Device Operating Voltage Options: ❐ MoBL Clock M3000 Family: 1.8V ❐ MoBL Clock M6000 Family: 2.5V, 3.0V, or 3.3V ■ Selectable clock output voltages for both MoBL Clock M3000

Contextual Info: Clock Oscillators Surface Mount Type KC2520A-C1 Series KC2520 Series CMOS / 1.8V / 2.5x2.0mm Features • Miniature ceramic package • Highly reliable with seam welding • CMOS output • Supply voltage VDD =1.8V Lower voltage available Table 1 Operating

Contextual Info: Clock Crystal Oscillators Surface Mount Type SAW Oscillators FSO-2B CMOS / 1.8V / 7.0x5.0A Features • Low Voltage 1.8V • Low Jitter • LV-CMOS Output • Operation at Fundamental High Frequency Table1 Standard Frequencies Frequencies MHz 100 106.25