Untitled
Abstract: No abstract text available
Text: S P L D 803B 4 GS 160-ch SEG and 80-ch COM Driver OCT. 15, 2004 Version 1.0 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. is believed to be accurate and reliable. Information provided by SUNPLUS TECHNOLOGY CO.
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160-ch
80-ch
SPLD803B
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IC 7411 DATA SHEET
Abstract: z035 DE Z042 0x83CC 4/Z0 607 MA GP 652 Z010 TADM04622 AE Z027 741 IC data sheet z02d
Text: Data Sheet August 18, 2004 MARS 2G5 P-Pro TDAT162G52 SONET/SDH 155/622/2488 Mbits/s Data Interface Features • ■ ■ ■ One of the next-generation, system-on-a-chip devices of Agere Systems’ multiservice access & rate solutions MARSTM family of framers.
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TDAT162G52)
STS-12/STM-4,
STS-48/STM-16.
DS02-197SONT
IC 7411 DATA SHEET
z035
DE Z042
0x83CC
4/Z0 607 MA GP 652
Z010
TADM04622
AE Z027
741 IC data sheet
z02d
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Untitled
Abstract: No abstract text available
Text: SPLD803B 4 GS 160-ch SEG and 80-ch COM Driver MAR. 07, 2005 Version 1.1 Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document.
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SPLD803B
160-ch
80-ch
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CT1F
Abstract: str 765 RT XAPP230 XAPP233 delay balancing in wave pipeline virtex user guide 1999 CAT16-LV4F12 CAT16-PT4F4 CLK180 virtex7
Text: Application Note: Virtex-E Family R XAPP233 v1.0 December 21, 1999 Multi-channel 622 MHz LVDS Data Transfer with Virtex-E Devices Application Note: Brian Von Herzen, Ph.D. & Jon Brunetti Summary The Virtex-E FPGA Series provides dedicated on-chip differential receivers between adjacent
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XAPP233
CT1F
str 765 RT
XAPP230
XAPP233
delay balancing in wave pipeline
virtex user guide 1999
CAT16-LV4F12
CAT16-PT4F4
CLK180
virtex7
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STM-16
Abstract: VSC8132
Text: VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Features • 2.488Gb/s 1:32 Demultiplexer • 77.76, 51.84, and 38.88MHz TTL Clock Outputs • SONET STS-48/SDH STM-16 • Single 3.3V supply • HSPECL Differential Serial Data and Clock
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VSC8132
488Gb/s
88MHz
STS-48/SDH
STM-16
32-Bit
128-Pin
VSC8132
STM-16
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lvds connectors pin assignments
Abstract: cna 450 spice simulation
Text: May 2001, ver. 1.0 Introduction LVDS Signaling Using APEX Device I/O Pins Application Note 138 Density increases in programmable logic devices PLDs have led users to integrate more functions into today's PLDs. This increase in functionality has allowed PLDs to play a major role in transmitting data between
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TIA/EIA-644
lvds connectors pin assignments
cna 450
spice simulation
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VSC8132
Abstract: STM-16 CLK38
Text: VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Features • 2.488Gb/s 1:32 Demultiplexer • 77.76, 51.84, and 38.88MHz TTL Clock Outputs • SONET STS-48/SDH STM-16 • Single 3.3V supply • HSPECL Differential Serial Data and Clock
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VSC8132
488Gb/s
88MHz
STS-48/SDH
STM-16
32-Bit
128-Pin
VSC8132
STM-16
CLK38
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