C20I Search Results

FUSE f10l 250v

Abstract: ADJUSTABLE VOLTAGE AND CURRENT REGULATOR 12v 30a lambda LMS Zener C218 fbt 073 12v to 230v inverters circuit diagrams sfbt-00 FBL-00-243 FBL-00 FBM-Z
Contextual Info: INSTRUCTION MANUAL FOR REGULATED POWER SUPPLY LL S-7000 SERIES This manual provides instructions intended for the operation of Lambda power supplies, and is not to be reproduced without the written consent of Lambda Electronics. All information contained herein

bfp760

Abstract: ADSP-TS201 reverse carry addition WPCT ADSP-21263 C-15 ts101 dsp application note boot kernel for the ADSP-21369 xr120xddddcccc "vector instructions" saturation
Contextual Info: ADSP-TS201 TigerSHARC Processor Programming Reference Revision 1.1, April 2005 Part Number 82-000810-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express

GR-253-CORE

Abstract: STM16 STM-16 ZL30406 ZL30406QGC ZL30406QGG1 CML termination 50 Ohm external termination volt
Contextual Info: ZL30406 SONET/SDH Clock Multiplier PLL Data Sheet Features March 2006 • Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

GR-1244-CORE

Abstract: ZL50015 ZL50015GAC ZL50015QCC ZL50015QCC1
Contextual Info: ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features • January 2006 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and

ZL50011QCG1

Abstract: GR-1244-CORE MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack

ZL50010

Abstract: TFR1M GR-1244-CORE MS-026
Contextual Info: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15

Contextual Info: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features September 2011 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • February 2005 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates •

Contextual Info: MT90401 SONET/SDH System Synchronizer Product Brief PB5429 Features • • • • • • • • • • • Meets requirements of Telcordia GR-253-CORE for SONET internal clocks and GR-1244-CORE for Stratum 3 clocks Meets requirements of ITU-T G.813 Option 1

C155N

Abstract: C155P GR-1244 GR-253 MT90401 ZL30402 ZL30407
Contextual Info: ZL30407 SONET/SDH Network Element PLL Data Sheet Features • • • • • • • • • • • April 2003 Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks SMC Meets requirements of GR-1244 for Stratum 3 Meets requirements of G.813 Option 1 and 2 for

GR-1244-CORE

Abstract: ZL50019 ZL50019GAC ZL50019QCC
Contextual Info: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps

GR-1244-CORE

Abstract: MS-026 ZL50011 11CH marking
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

GR-1244-CORE

Abstract: ZL50018 ZL50018GAC ZL50018QCC 99 mfu
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

GR-1244-CORE

Abstract: GR-253-CORE ZL30106 ZL30106QDG "network interface cards"
Contextual Info: ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • • • • • • • • October 2004 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH

C155

Abstract: C155N C155P GR-1244 GR-253 MT90401 ZL30402
Contextual Info: ZL30402 SONET/SDH Network Element PLL Data Sheet Features • • • • • • • • • • • March 2003 Meets requirements of GR-253 for SONET stratum 3 and SONET Minimum Clocks SMC Meets requirements of GR-1244 for stratum 3 Meets requirements of G.813 Option 1 and 2 for

GR-1244-CORE

Abstract: GR-253-CORE MT90401 OC48 STM-16 ZL30406
Contextual Info: ZLAN-34 Applications of the ZL30406 and MT90401 SONET/SDH Linecard Solutions Application Note Contents August 2003 1.0 1.0 Summary 2.0 SONET/SDH Linecard Solutions 2.1 SONET/SDH Linecard requirements 2.2 MT90401 + ZL30406 Solution 2.2.1 Introduction 2.2.2 Design Considerations

C155

Abstract: C155N C155P GR-1244 GR-253-CORE ZL30410 ZL30410QCC ZL30410QCG1
Contextual Info: ZL30410 Multi-service Line Card PLL Data Sheet Features • • • • • • • • • November 2006 Generates clocks for OC-3, STM-1, DS3, E3, DS2, DS1, E1, 19.44 MHz and ST-BUS Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 DS2 , E1 and DS1 interfaces

ZL50018

Abstract: GR-1244-CORE ZL50018GAC ZL50018QCC MFU 78
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

Contextual Info: 30 to 200MHz Microwave Coil Components Relay Header C L 360 □ GENERAL FEA TU RES The M C -200 R C Series Microwave Coil Com ponent highest reliability over long periods. A Teflon (T R ) (with relay header) is a 2.54-m m (.1") pitch com pact sheet device

stm cl-90

Abstract: GR-1244 GR-253 MT90401 ZL30402 ZL30407 ZL30407QCC ZL30410 G735
Contextual Info: ZL30407 SONET/SDH Network Element PLL Data Sheet Features March 2004 • Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks SMC • Meets requirements of GR-1244 for Stratum 3 • Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC)

GR-253-CORE

Abstract: MT90401 ZL30407 ZL30415 ZL30415GGC
Contextual Info: ZL30415 SONET/SDH Clock Multiplier PLL Data Sheet Features June 2004 • Meets jitter requirements of Telcordia GR-253CORE for OC-12, OC-3, and OC-1 rates • Meets jitter requirements of ITU-T G.813 for STM4, and STM-1 rates • Provides one differential LVPECL output clock

iball

Abstract: transistor oc 76 GR-253-CORE OC48 STM16 STM-64 ZL30416 ZL30416GGG
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features June 2004 • Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE • Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in

ECTF

Abstract: MS-026 MT90866 MT90866AG MVIP-90 Compact PCI Backplane Block Diagram
Contextual Info: MT90866 WAN Access Switch Product Brief Features PB5381 ISSUE 3 May 2000 Ordering Information • • • • • • • • • • • • • • • • • • • • • • • • 3.3V operation with 5V tolerant inputs and I/O’s 2,432 x 2,432 channel non-blocking switching

Contextual Info: MT90401 SONET/SDH System Synchronizer Data Sheet Features November 2003 • Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock • Meets requirements of GR-1244-CORE Stratum 3 • Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks SEC with external