BUS CONTROLLER Search Results

BUS CONTROLLER Result Highlights (5)

Part	Manufacturer	Description
GRT155C81A475ME13D	Murata Manufacturing Co Ltd	AEC-Q200 Compliant Chip Multilayer Ceramic Capacitors for Infotainment
GRT155C81A475ME13J	Murata Manufacturing Co Ltd	AEC-Q200 Compliant Chip Multilayer Ceramic Capacitors for Infotainment
GRT155D70J475ME13D	Murata Manufacturing Co Ltd	AEC-Q200 Compliant Chip Multilayer Ceramic Capacitors for Infotainment
GRT155D70J475ME13J	Murata Manufacturing Co Ltd	AEC-Q200 Compliant Chip Multilayer Ceramic Capacitors for Infotainment
D1U74T-W-1600-12-HB4AC	Murata Manufacturing Co Ltd	AC/DC 1600W, Titanium Efficiency, 74 MM , 12V, 12VSB, Inlet C20, Airflow Back to Front, RoHs

BUS CONTROLLER Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: Interrupt controller 16-bit peripheral data bus Peripheral address bus 16-bit internal Y data bus Internal Y address bus Internal X address bus CPU 16-bit internal X data bus 32-bit internal data bus CDB Buffer Internal address bus (CAB) ROM Block Diagram	Original	16-bit 32-bit 64-bit	PDF
SH7615 Abstract: bus ethernet Hitachi DSA0084 Text: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller DSP Hitachi user debug interface X-RAM Serial I/O Serial communication interface	Original	16-bit 32-bit SH7615 SH7615 bus ethernet Hitachi DSA0084	PDF
SH7706 Abstract: No abstract text available Text: Block Diagram MMU L bus I bus 1 TLB CPU UBC CCN AUD SCI Peripheral bus 1 1.2 TMU CACHE RTC BRIDGE BSC SCIF DMAC CPG/WDT CMT Peripheral bus 2 INTC I bus 2 H-UDI ADC DAC External bus interface Legend ADC : A/D converter AUD : Advanced user debugger BSC : Bus state controller	Original	SH7706	PDF
"Ethernet Controller" Abstract: Hitachi DSA0084 SH7616 controller Text: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller Serial I/O with FIFO DSP Hitachi user debug interface X-RAM Serial I/O Serial communication	Original	16-bit 32-bit SH7616 "Ethernet Controller" Hitachi DSA0084 SH7616 controller	PDF
pin diagram priority decoder 74138 Abstract: 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D uPB8289 8284 clock intel 8289 8289 bus arbiter Text: SEC mPB8289 BUS ARBITER NEC Electronics Inc. D escription Pin C onfiguration The /j P B8289 bus arbiter is used with the/iPB8288 bus controNer to interface 8086 and 8088 microprocessors to a multi master system bus. The fiPB8289 controls the ¿iPB8288 bus controller and the bus transceivers	OCR Scan	uPB8289 the/iPB8288 fiPB8289 iPB8288 PB8289 pin diagram priority decoder 74138 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D 8284 clock intel 8289 8289 bus arbiter	PDF
Untitled Abstract: No abstract text available Text: Chapter 5 Bus Operations The TurboSPARC microprocessor contains four bus controllers along with four dedicated bus interfaces. 1. Secondary cache bus interface and controller 2. Main memory DRAM bus interface and controller 3. SBus interface and controller	Original	64-bit 28-bit	PDF
1553 bus controller Abstract: BUS-65515 DDC 1553 BUS-65600 Text: D D C BUS-65600 ILC DATA DEVICE CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES • BUS-65600 is available as MIL-DWG DESC 5962-88585-01XC. DESCRIPTION The BUS-65600 is a dual redundant MIL-STD-1553 Bus Controller (BC), Re	OCR Scan	BUS-65600 MIL-STD-1553 BUS-65600 5962-88585-01XC. MIL-STD1553 BUS-63125, 1553 bus controller BUS-65515 DDC 1553	PDF
Untitled Abstract: No abstract text available Text: ^ 001 4, x y BUS-65610 _ ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged	OCR Scan	BUS-65610 MIL-STD-1553 BUS-65610 BUS-63125, BUS-65600 BUS-65612	PDF
0xF008 Abstract: all ic data high level block diagram for i2c controller S5N8946 Text: I2C BUS CONTROLLER S5N8946 ADSL/CABLE MODEM MCU 6 I2C BUS CONTROLLER OVERVIEW The S5N8946′s internal IC bus (I2C-bus) controller has the following important features: — It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I2C-bus is free,	Original	S5N8946 S5N8946s 0xf00c 0x00000000 16-bit 0xF008 all ic data high level block diagram for i2c controller	PDF
Z80 i2c INTERFACING Abstract: intel 8049 8051 using I2C BUS PCA9564 intel 8051 architecture PCA9564 Intel 8051 20 MHz PCA9564BS-T motorola 6800 datasheet z80 intel 8051 microcontroller architecture Text: NXP I2C-bus and Bus controller PCA9564 Easy interfacing between serial I2C-bus and 8-bit parallel communication bus This simple-to-use bus controller makes it easy to create a bidirectional interface between the serial I2C-bus and the 8-bit parallel bus system used by most standard microcontrollers and	Original	PCA9564 80C51 PCA9564D PCA9564D-T PCA9564PW PCA9564PW-T PCA9564BS-T Z80 i2c INTERFACING intel 8049 8051 using I2C BUS PCA9564 intel 8051 architecture PCA9564 Intel 8051 20 MHz PCA9564BS-T motorola 6800 datasheet z80 intel 8051 microcontroller architecture	PDF
4038X Abstract: BUS-27765 BUS-65201 590i4 A5690 BUS-65101 BUS-66106 BUS-66111 Text: 0 0 BUS-661068a n d BUS-66111 ILC DATA DEVICE CORPORATION MIL-STD-1553 BUS CONTROLLER PROTOCOL HYBRIDS BUS-66106 FEATURES • GENERATES PROTOCOL, TIMING AND CONTROL FOR MIL-STD-1553 OR MACAIR A5690 BUS CONTROLLER • SUPPORTS ALL MESSAGE FORMATS DESCRIPTION	OCR Scan	BUS-661068and BUS-66111 BUS-66106 BUS-66106 BUS-66111 MIL-STD-1553 A5690. BUS-66111-883B 4038X BUS-27765 BUS-65201 590i4 A5690 BUS-65101	PDF
BUS-65201 Abstract: No abstract text available Text: QOQ BUS-66106*a n d BUS-66111 ILC DATA DEVICE CORPORATION MIL-STD-1553 BUS CONTROLLER PROTOCOL HYBRIDS BUS-66106 FEATURES • GENERATES PROTOCOL, TIMING AND CONTROL FOR MIL-STD-1553 OR MACAIR A5690 BUS CONTROLLER • SUPPORTS ALL MESSAGE FORMATS DESCRIPTION	OCR Scan	BUS-66106 BUS-66111 BUS-66106 MIL-STD-1553 A5690 BUS-66111 BUS-66111-883B BUS-66106-883B BUS-65201	PDF
F8H SMD Abstract: DIP20 HVQFN20 JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665 SO20 Text: PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 03 — 12 August 2008 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus	Original	PCA9665 PCA9665 PCA9564 F8H SMD DIP20 HVQFN20 JESD22-A114 JESD22-A115 JESD78 SO20	PDF
DIP20 Abstract: HVQFN20 JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665 SO20 Text: PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 02 — 7 December 2006 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus	Original	PCA9665 PCA9665 PCA9564 DIP20 HVQFN20 JESD22-A114 JESD22-A115 JESD78 SO20	PDF

F8H SMD Abstract: No abstract text available Text: PCA9665; PCA9665A Fm+ parallel bus to I2C-bus controller Rev. 4 — 29 September 2011 Product data sheet 1. General description The PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus	Original	PCA9665; PCA9665A PCA9665/PCA9665A PCA9665 PCA9665A F8H SMD	PDF
bck-01 Abstract: RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 BUS-65600 A09 N03 BUS-65610 Text: □01 4, > 7 BUS-65610 _ ILC DATA DEVICI CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR APPROX. Vs ACTUAL SIZE FEATURES • DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit	OCR Scan	BUS-65610 MIL-STD-1553 BUS-65610 BUS-63125, BUS-65600 BUS-65612 bck-01 RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 A09 N03	PDF
PIN DIAGRAM OF 80286 Abstract: kc 4369 SAB 80287 82C206 CHIPset for 80286 80287 80286 data bus MD sab82c206 82c206 ipc 80286 chipset Text: SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset 4-342 March 1990 Siemens Components, Inc. SAB 82C211 • SAB 80286 bus interface and bus control • CPU/AT bus state machine and bus arbitration logic • Clock generator with software speed selection logic optional independent AT	OCR Scan	82C211 82C211 82C215 84-pin PL-CC-84) PIN DIAGRAM OF 80286 kc 4369 SAB 80287 82C206 CHIPset for 80286 80287 80286 data bus MD sab82c206 82c206 ipc 80286 chipset	PDF
MPC561 Abstract: MPC563 IMB3 Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	IML18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 MPC561 MPC563 IMB3	PDF
MPC566 Abstract: MPC565 NOTES ON MULTIPLEXER Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 MPC566 MPC565 NOTES ON MULTIPLEXER	PDF
MPC555 Abstract: 7f90 Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	MPC555 MPC555 7f90	PDF
Motorola MPC555 Abstract: MPC555 MPC556 Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	KLVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 Motorola MPC555 MPC555 MPC556	PDF
MPC556 Abstract: MPC555 7fa0 Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31 MPC556 MPC555 7fa0	PDF
MPC555 Abstract: No abstract text available Text: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.	Original	IRQ17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 MPC555	PDF
SAB82C206 Abstract: No abstract text available Text: SIEMENS SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset Advance Information 117 3.90 SAB 82C211 • SAB 80286 bus interface and bus control • • • CPU/AT bus state machine and bus arbitration logic • Clock generator with software speed selection logic optional independent AT	OCR Scan	82C211 82C215 84-pin SAB82C206	PDF

BUS CONTROLLER Search Results

BUS CONTROLLER Result Highlights (5)

BUS CONTROLLER Datasheets Context Search

Untitled

SH7615

SH7706

"Ethernet Controller"

pin diagram priority decoder 74138

Untitled

1553 bus controller

Untitled

0xF008

Z80 i2c INTERFACING

4038X

BUS-65201

F8H SMD

DIP20

F8H SMD

bck-01

PIN DIAGRAM OF 80286

MPC561

MPC566

MPC555

Motorola MPC555

MPC556

MPC555

SAB82C206