BUFFERING Search Results

CAD15-CAD8

Contextual Info: PCI1250A PC CARD CONTROLLER XCPS014 -D E C E M B E R 1997 * Peripheral Component Interconnect PCI Power Management Compliant • Supports Zoom Video With Internal Buffering • ACP11.0 Compliant • Programmable Output Select for CLKRUN • Packaged in 256-Pin BGA

Contextual Info: TEXAS INSTR A S I C / M E M O R Y b4E D • 8^1725 ODflEbCH 3 3b M J I SN74ABT7816 64 X 36 X 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS129-JULY1992 Free-Running CLKA and CLKB May Be Asynchronous or Coincident Two Independent 64 x 36 Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

UM82450

Contextual Info: UMC UM82450 Asynchronous Communication — Element ACE Mi Feature • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data stream ■ Full double buffering eliminates need for precise synchronization ■ Independently controlled transmit, receive, I ine status,

Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

bav40

Abstract: IP4778CZ38 TSSOP38
Contextual Info: IP4778CZ38 HDMI ESD protection, DDC buffering and hot plug control Rev. 02 — 12 February 2009 Product data sheet 1. General description The IP4778CZ38 is designed for HDMI receiver host interface protection. The IP4778CZ38 includes DDC buffering, slew rate acceleration and decoupling, Hot Plug

EL5127

Abstract: EL5127CY EL5127CY-T13 EL5127CY-T7 EL5227 EL5227CL EL5227CL-T7 EL5327 EL5427
Contextual Info: EL5127, EL5227, EL5327, EL5427 Data Sheet 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers The EL5127, EL5227, EL5327, and EL5427 are low power, high voltage rail-to-rail input/output buffers designed for use in reference voltage buffering applications

D827

Abstract: SMD d827 54ACTQ827 54ACTQ827DMQB 54ACTQ827FMQB 54ACTQ827LMQB AM29827
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 07/16/96 Last Update Date: 03/09/99 Last Major Revision Date: 12/17/98 MN54ACTQ827-X REV 2A0 10-Bit Buffer/Line Driver with TRI-STATE Outputs General Description The ACTQ827 10-bit bus buffer provides high performance bus interface buffering for wide

EL5224

Abstract: EL5224IL EL5224IL-T13 EL5224IL-T7 EL5224IRE EL5224IRE-T7 EL5324 EL5424
Contextual Info: EL5224, EL5324, EL5424 Data Sheet 12MHz Rail-to-Rail Buffers + 100mA VCOM Amplifier The EL5224, EL5324, and EL5424 feature 8, 10, and 12 low power buffers, respectively, and one high power output amplifier. They are designed primarily for buffering column driver reference voltages in TFT-LCD

4 channel RF modulator

Contextual Info: &TDK. TSC 79W2525 AVPro Video Filter/Modulator TDK SEMICONDUCTOR CORP. T a r g e t S p e c i f ic a t i o n October 1996 GENERAL DESCRIPTION FEATURES The 79W2525 AVPro™ is a low cost, high performance IC that performs video filtering/buffering and modulation

EL5224

Abstract: EL5224IL EL5224IL-T13 EL5224IL-T7 EL5224ILZ EL5224ILZ-T7 EL5324 EL5424
Contextual Info: EL5224, EL5324, EL5424 Data Sheet May 11, 2005 12MHz Rail-to-Rail Buffers + 100mA VCOM Amplifier The EL5224, EL5324, and EL5424 feature 8, 10, and 12 low power buffers, respectively, and one high power output amplifier. They are designed primarily for buffering column

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

sf 127d

Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction

Contextual Info: FAST CMOS 20-BIT BUFFER Júáá$«#JA IDT54/74FCT16827AT/BT/CT/ET FEATURES: D E S C R IP TIO N : - The FCT16827AT/BT/CT/ET 20-bit buffers are built using advanced dual metal CMOS technology. These 20-bit bus drivers provide highperformance bus interface buffering for wide data/address paths or buses

Contextual Info: HITTITE MICROWAVE CORPORATION FEBRUARY 1995 GaAs MMIC Buffered C-Band VCO Features HMC131 il 1 GHz TUNING RANGE . . SINGLE +5V SUPPLY OPERATION NO EXTERNAL VARACTOR REQUIRED General Description The HMC131 chip is a C-Band VCO with onchip buffering for improved load isolation. It

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A

Contextual Info: CMOS SyncFIFO IDT723611 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B

Contextual Info: 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - The LVC162827A 20-bit buffer is built using advanced dual metal CMOS technology. The 20-bit bus driver provides highperformance bus interface buffering for wide data/address paths or busses carrying parity. Two pair of NAND-ed output enable

Contextual Info: IDT74FCT163827A/B/C 3.3V CMOS 20-BIT BUFFERS Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 0.5 M IC RO N CM O S Technology The FCT163827A/B/C 20-bit buffers are built using ad­ vanced dual metal CM O S technology. These 20-bit bus drivers provide high-performance bus interface buffering for

Contextual Info: FAST CMOS 16-BIT BUFFER/LINE DRIVER Integrated Device Technology, Inc. IDT54/74FCT16244T/AT/CT/ET IDT54/74FCT162244T/AT/CT/ET IDT54/74FCT166244T/AT/CT IDT54/74FCT162H244T/AT/CT/ET ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: The 16-Bit Buffer/Line Driver isforbus interface orsignal buffering

SN74ABT3611

Abstract: mdv 434
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC B S 127C - JULY 1992 - RE V IS E D A P R IL 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Empty Flag EF and Almost-Empty Flag (AE) Synchronized by CLKB 64 x 36 Clocked FIFO Buffering Data From

ir911

Abstract: A14C A15C A25C A26C SN74ACT3631 SN74ACT3641 SN74ACT3651
Contextual Info: SN74ACT3641 1024x36 CLOCKED FIRST-IN, FIRST-OUT MEMORY S CAS338A - JANUARY 1994 - RE V IS E D JUNE 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 x 36 Synchronous Read Retransmit Capability

National Semiconductor PC16550D UART

Abstract: K2687 CL-GD5465 VR5000 PC16550D R5000 VRC5074 R4311 H49-M97 CL-GD546
Contextual Info: VRC5074 System Controller June 1998 Data Sheet 1.0 Introduction 1.1 The VRC5074 System Controller is a software-configurable chip that directly connects the V R5000 CPU to SDRAM memory, a PCI Bus, and a Local Bus, without external logic or buffering. From the CPU’s viewpoint, the controller acts as a memory controller, DMA controller, PCI-Bus host bridge, and Local-Bus host bridge. From the viewpoint of PCI agents, the controller acts as master and target on the PCI Bus. The