BUFFER SCRAMBLER Search Results

CMX878

Abstract: Descrambler
Contextual Info: Tx Output Buffer MOD Tx Level Control Scrambler Enable LOCAL ANALOGUE LOOPBACK Descrambler Enable Rx Gain Control + MODEM ENERGY DETECTOR CMX878 Block Diagram - BIAS RXIN RXFB Rx Input Amplifier

Voice Activity Detector

Abstract: PCM encoder VOICE SCRAMBLER activity diagram audio scrambler CMX649 encoder/decoder Scrambler Voice Detector pcm decoder
Contextual Info: Mic. In ADM Encoder Buffer PCM Encoder Voice Activity Detector Programmable Anti-Alias Filter Input Level VDD Input Coded Signal VBIAS Scrambler Tx Data Encode VAD VSS Serial Clock Coding Algorithm Selections Transcoder C-BUS Serial I/O Control Registers Command Data

DIODE S4 72A

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD 1.25V (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.8V TO 3.3V) FD_B Rev. B SIGNAL MONITOR 14 VIN+B VIN–B DDC ADC CORE BUFFER CONTROL REGISTERS V_1P0 SIGNAL MONITOR CLOCK GENERATION

LAN89303

Abstract: LAN89303AM 56-PIN AEC-Q100 obd connector ic 7432 encoder
Contextual Info: LAN89303AM Three Port 10/100 Managed Ethernet Switch with MII/RMII for Automotive Applications PRODUCT FEATURES Datasheet — Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory

MA8121

Abstract: AD10 AD11 MD10 MD11 MX98726
Contextual Info: ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space

MAR7

Abstract: MD11 MD14 MX98726
Contextual Info: ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space

LAN89303

Abstract: LAN89303AM cd 8227 gp
Contextual Info: LAN89303AM Three Port 10/100 Managed Ethernet Switch with MII/RMII for Automotive Applications PRODUCT FEATURES Datasheet — Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory

micrel KS8995

Abstract: KS8995 ks8995e YCL PH406466 802.1q trunk HB726-1 AT24C01A H1164 HB826-2 micrel mii
Contextual Info: KS8995E Micrel KS8995E 5-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 1.10 On the media side, the KS8995E supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced

558-5999-q9

Abstract: PH406466 PACKAGE Delta LF8731 KS8999 factory test 5 port
Contextual Info: KS8999 Micrel KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.14 KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset

KSZ8893MQL application note

Abstract: KSZ8893MQL
Contextual Info: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.5 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer

IP113

Abstract: IP113A IP113-DS-P07 93C46 QFP-128L 30 PIN duplex led display
Contextual Info: IP113 10/100 Base-Tx / Fx Converter Feature Utilize single clock source only 25Mhz 2 port 10/100 Ethernet switch with built in transceivers Utilize single power (2.5v) and memory 0.25um technology Build in SSRAM for frame buffer Packaged in 128 pin PQFP

KS8997

Abstract: ksz8997 AT24C01A H1102 H1164 KS8995X 10BaseTX MICREL PQFP DATE CODE
Contextual Info: KS8997/KSZ8997 8-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev 1.1 General Description The KS8997 contains eight 10/100 physical layer transceivers, eight MAC Media Access Control units with an integrated layer 2 switch. The device runs as

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD 1.25V (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) BUFFER Rev. 0 DDC FD 4 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± CONTROL REGISTERS V_1P0 FAST DETECT ÷2 ÷4 ÷8 AGND

KSZ8893MQL application note

Abstract: TLA-6T718 KSZ8893-MQL MDIO clause 45 specification KSZ8893 UPS052 KSZ8893 MII KSZ8893MQL KS8893MQLI KS8893MQL
Contextual Info: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.6 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer

Delta LF8731

Abstract: Bel 188 ct diagram LF8731 558-5999-Q9 AT24C01A H1164 HB826-2 KS8999 KS8999I PH406466
Contextual Info: KS8999 Micrel KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.12 KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset

KSZ8893MQL application note

Abstract: "clock collision" KSZ8893MQL
Contextual Info: KSZ8893MQL/MQLI Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.3 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer

KSZ8893-MQL

Abstract: KS8893M MAG-JACK KSZ8893MQL application note KSZ8893 KSZ8893 MII TLA-6T718 KSZ8893MBL 10LINK LSE B3 transformer
Contextual Info: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.5 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer

Contextual Info: KS8997/KSZ8997 8-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev 1.1 General Description The KS8997 contains eight 10/100 physical layer transceivers, eight MAC Media Access Control units with an integrated layer 2 switch. The device runs as

RJ754-C-NL

Abstract: 16Kx32 pulse h1012 HB614-1 KS8993 RJ754 reverse MII timing YCL Transformer PH406080 KSZ8993
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

IP175D

Abstract: IP175 IP175 D IP175 datasheet 7 segment display duplex led type QFP-128L 14880 h60 buffer 93C46 05h12
Contextual Info: IP175 5 Port 10/100 Ethernet Integrated Switch Feature Utilize single clock source only 25Mhz 5 port 10/100 Ethernet switch with built in transceivers Utilize single power (2.5v) and memory 0.25um technology Build in SSRAM for frame buffer Packaged in 128 pin PQFP

Contextual Info: MX98728AEC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs

KS8993

Abstract: RJ754-C-NL KS8993I PV32 ycl 20pmt04 center tap transformer pulse h1012
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.04 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

MA17

Abstract: MA18 MX98728EC Macronix marking GMAC
Contextual Info: MX98728EC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs

Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through