BLOCK DIAGRAM OF PECL TO TTL Search Results

Contextual Info: VSC834 Data Sheet FEATURES ● ● ● ● ● 17 input by 17 output crosspoint switch 2.7 Gbps NRZ data bandwidth 46 Gbps aggregate bandwidth TTL-compatible µP interface Differential PECL data inputs ● ● ● ● ● On-chip 50 Ω input terminations

lcd Voltmeter

Abstract: CXA3197 HI3197 HI3197JCQ C2274
Contextual Info: HI3197 Data Sheet October 1998 10-Bit, 125 MSPS D/A Converter • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits • Conversion Rate HI3197JCQ -20 to 75 125 MSPS PECL 100 MSPS (TTL) • Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL

PRL-426TTR

Abstract: PRL-426N PRL426PTR PRL-426T PRL-426 sma
Contextual Info: PRL-426N DUAL CHANNEL NECL TO LVDS TRANSLATOR PRL-426P DUAL CHANNEL PECL TO LVDS TRANSLATOR PRL-426T DUAL CHANNEL TTL TO LVDS TRANSLATOR APPLICATIONS • Converting Single Ended or Differential NECL/PECL Signals to LVDS Signals • Converting TTL Signals to LVDS

Contextual Info: VITESSE G-TAXIchips VSC7101 /V5C7 702/VSC7103/VSC7 704 1.25 Gbits/sec Data Communications Chipset G-TAXICHIP FEATURES • Compatible with ANSI X3T9.3 Fiber Channel Standard • Up to 1.25 Gbits/sec serial data rate • 32 or 40-bit wide parallel TTL data bus input

AZ100ELT23

Contextual Info: AZ100ELT23 Dual Differential PECL to CMOS/TTL Translator www.azmicrotek.com DESCRIPTION The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate

AZ100ELT20

Abstract: ARIZONA MICROTEK MLP8
Contextual Info: AZ100ELT20 CMOS/TTL to Differential PECL Translator www.azmicrotek.com DESCRIPTION FEATURES The AZ100ELT20 is a CMOS/TTL to differential PECL translator. It operates with a single power supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications. The extremely

ARIZONA MICROTEK

Abstract: MARKING HT23
Contextual Info: AZ100ELT23 Dual Differential PECL to CMOS/TTL Translator www.azmicrotek.com DESCRIPTION The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate

AZ100ELT22

Abstract: ARIZONA MICROTEK
Contextual Info: AZ100ELT22 Dual CMOS/TTL to Differential PECL Translator DESCRIPTION The AZ100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of

COMMAND40

Contextual Info: VITESSE VSC7103/V5C7104 High Performance M u x /D e m u x Chipset for Fibre Channel or Proprietary Serial Links MUX/DMUX FEATURES • Parallel 32 or 40-bit wide TTL bus interface • 32 or40-to-10 mux • 10-to-32 or 40 demux • Encode/decode functions and special

AZ100ELT21

Abstract: ARIZONA MICROTEK
Contextual Info: AZ100ELT21 Differential PECL to CMOS/TTL Translator DESCRIPTION The AZ100ELT21 is a differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the single gate of the

F100K

Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 Block Diagram Features      0.5ns Typical Propogation Delay <100ps Typical Output to Output Skew Flow Through Pinouts Differential PECL Output RoHS Compliant Pb Free Packages

93C46

Abstract: ML6510 ML6510CQ80
Contextual Info: www.fairchildsemi.com ML6510 Series Programmable Adaptive Clock Manager PACMan Features General Description • Input clocks can be either TTL or PECL with low input to output clock phase error • 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip)

ttl 741

Contextual Info: Advance Product Information 2.5 Gbits/sec Dual 2x2 Crosspoint Switch VSC830 Features • Dual 2x2 Crosspoint Switch • PECL Compatible Output Driver • 2.9 Gbits/sec NRZ Data Bandwidth, 2.9 GHz Signal Bandwidth • PECL/TTL Compatible Control Inputs • Back-terminated Output Driver

AZM100ELT20

Abstract: AZHLT20 AZ100ELT20 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2
Contextual Info: ARIZONA MICROTEK, INC. AZ10ELT20 AZ100ELT20 CMOS/TTL to Differential PECL Translator PACKAGE AVAILABILITY FEATURES • • • • • • 0.5ns Typical Propagation Delay Differential PECL Outputs Flow Through Pinouts Operating Range of 3.0V to 5.5V Direct Replacement for ON Semiconductor

Contextual Info: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

AZ100ELT20

Abstract: AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2 MC100ELT20 MC10ELT20
Contextual Info: ARIZONA MICROTEK, INC. AZ10ELT20 AZ100ELT20 CMOS/TTL to Differential PECL Translator PACKAGE AVAILABILITY FEATURES • • • • • • 0.5ns Typical Propagation Delay Differential PECL Outputs Flow Through Pinouts Operating Range of +3.0V to +5.5V Direct Replacement for ON Semiconductor

H607

Abstract: SY100H607 SY100H607JC SY10H607 SY10H607JC SY10H607JCTR
Contextual Info: REGISTERED HEX PECL-TO-TTL FEATURES DESCRIPTION Differential PECL data and clock inputs 48mA sink, 15mA source TTL outputs Single +5V power supply Multiple power and ground pins to minimize noise Specified within-device skew VBB output for single-ended use

Contextual Info: * SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • PECL version of popular ECLinPS E111 ■ Low skew ■ Guaranteed skew spec ■ V bb output ■ TTL enable input ■ Selectable TTL or PECL clock input ■ Single +5V supply

Contextual Info: SYNERGY SEMICONDUCTOR SINGLE SUPPLY PECL Clockworks 1:9 CLOCK DRIVER " " ly 'S i FEATURES DESCRIPTION • PECL version of popular ECLinPS E111 ■ Low skew ■ Guaranteed skew spec ■ V bb output ■ TTL enable input ■ Selectable TTL or PECL clock input

wo-04

Abstract: F100K SY100S391 SY100S391DC SY100S391FC
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR r c ^ L . I riM lM o LA I U r i SYNERGY SEMICONDUCTOR FEATURES SY100S391 DESCRIPTION • Operates from a single +5V supply ■ Differential PECL outputs ■ ESD protection of 2000V The SY100S391 is a hex TTL-to-PECL translator for

F100K

Abstract: SY100S391 SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation