BIT MAPPER Search Results

GR-253

Abstract: TMPR28051
Contextual Info: Advisory August 5, 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.

25e5

Abstract: GR253-CORE GR-253 TMPR28051 VT13 GR-253 J0 byte length 14
Contextual Info: Advisory August 5, 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.

chn 648 equivalent

Contextual Info: Advisory April 1999 m ic ro e le c tro n ic s group Lucent Technologies Bell Labs Innovations TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 2 of the Device Known TMPR28051 Version 2 Issues Issue 1: Reset Bit The software reset bit (bit 0) of register 0x00 is not functional.

STS-192

Abstract: STS-48 VSC9112
Contextual Info: SONET/SDH IP/ATM Framer and Mapper Framers and Mappers VSC9112 Product Brief Features: System / Packet Interface • 32-bit Industry Compliant POS-PHY-3, Single-PHY Packet Interface • 32-bit Industry Compliant UTOPIA-3, Single-PHY Cell Interface Physical Layer Channelization

DMX chip

Abstract: DMX single chip controller STS-192 STS-48 VSC9142
Contextual Info: SONET/SDH IP/ATM Framer and Mapper VSC9142 Framers and Mappers Product Brief Features: System / Packet Interface • 32-bit Industry Compliant POS-PHY-3, Single-PHY Packet Interface • 32-bit Industry Compliant UTOPIA-3, Single-PHY Cell Interface Physical Layer Channelization

74612

Abstract: Memory Mapper 16x8-bit TDVS-H CFT6121A
Contextual Info: CFT6121A CFT6121A 74612 GENERAL DESCRIPTION: 4-TO 8-BIT MEMORY MAPPER CFT6121A is designed for paged memory mapping. It expands four address lines to eight address lines and contains a 16x8-bit RAM to story addresses. See the TI data book for a complete description.

hdlc

Abstract: PM5383 PM8316 E1 frame POS-PHY ATM format
Contextual Info: PM5383 S/UNI 12xJET Preliminary 12-Channel ATM and Bit HDLC User Network Interface MODES OF OPERATION FEATURES • Single chip 12-channel DS3/E3/J2 framer and ATM / bit-HDLC mapper into POS-PHY / UTOPIA interface. Each channel can be individually configured for the desired rate and

POS-PHY utopia

Abstract: POS-PHY ATM format hdlc E1 frame
Contextual Info: PM5386 S/UNI 4xJET Preliminary 4-Channel ATM and Bit HDLC User Network Interface MODES OF OPERATION FEATURES • Single chip 4-channel DS-3/E3/J2 framer and ATM/bit-HDLC mapper into POS-PHY/Utopia interface. Each channel can be individually configured for the desired rate and data format.

Contextual Info: ADS5296A www.ti.com SBAS631 – OCTOBER 2013 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter Check for Samples: ADS5296A FEATURES DESCRIPTION • The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter ADC with sample rates

Contextual Info: ADS5296A www.ti.com SBAS631 – OCTOBER 2013 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter Check for Samples: ADS5296A FEATURES DESCRIPTION • The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter ADC with sample rates

Contextual Info: ADS5296A www.ti.com SBAS631 – OCTOBER 2013 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter Check for Samples: ADS5296A FEATURES DESCRIPTION • The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter ADC with sample rates

74612

Abstract: 74610 CFT6120A
Contextual Info: CFT6120A CFT6120A 74612 GENERAL D ESC R IPTIO N : 4-TO 12-BIT MEMORY MAPPER CFT6120A is designed for paged memory mapping. It expands four address lines to 12 address lines and contains a 16xl2-bit RAM to story addresses. The user can easily make it into a 74610 or 74612 as fol­

n117

Contextual Info: DS3F Device DS3 Framer TXC-03401B DATA SHEET • DS3 payload access, bit-serial or nibble-parallel • C-bit parity or M13 operating mode • C-bit interface 13 C-bits in, 14 out • Detect and generate DS3 AIS, and idle signals • Transmit reference generator for serial operation

Contextual Info: ADS5296 www.ti.com SBAS606A – MAY 2013 – REVISED MAY 2013 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter Check for Samples: ADS5296 FEATURES DESCRIPTION • The ADS5296 is a low-power, 12-bit, 8-channel, analog-to-digital converter ADC with sample rates

Virtex-II Board

Abstract: LVCMOS15 vhdl code for flip-flop FG672 UG012
Contextual Info: R Single-Ended SelectI/O Resources VHDL Template: - Module: SIGNED_MULT_18X18 - Description: VHDL instantiation template - 18-bit X 18-bit embedded signed multiplier asynchronous - Device: Virtex-II Pro Family - Components Declarations

Contextual Info: BCM8501 PRODUCT Brief STS-192c/STM-64c B C M 8 5 0 1 POS FRAMER S U M M A R Y F E AT U R E S 16-bit 622-Mbps LVDS line interface compliant with • SFI-4 64-bit 200MHz HSTL system interface compliant with • SPI-4/Phase1 16-bit generic microprocessor interface for device

STM-64c

Abstract: bcm8124
Contextual Info: BCM8501 PRODUCT Brief STS-192c/STM-64c B C M 8 5 0 1 POS FRAMER S U M M A R Y F E AT U R E S • 416-bit 622-Mbps LVDS line interface compliant with SFI64-bit 200MHz HSTL system interface compliant with • SPI-4/Phase1 16-bit generic microprocessor interface for device control

JESD79-2B

Abstract: CR88 DDR2-667 STLS2E02 STLS2F01 STLS2F02 Loongson
Contextual Info: STLS2F02 high performance 64-bit superscalar MIPS Loongson 2F microprocessor Preliminary Data Features • 64-bit superscalar architecture ■ 900 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set

JESD79-2B

Abstract: CR88 DDR2 Mechanical Dimensions DDR2-667 STLS2E02 STLS2F01 STLS2F02 axi crossbar
Contextual Info: STLS2F02 high performance 64-bit superscalar MIPS Loongson 2F microprocessor Preliminary Data Features • 64-bit superscalar architecture ■ 900 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set

Loongson

Abstract: axi crossbar DDR2-667 JESD97 STLS2E02 STLS2F01
Contextual Info: STLS2F01 High performance 64-bit superscalar MIPS Loongson 2F: microprocessor Data Brief Features • 64-bit superscalar architecture ■ 900 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set

JESD79-2B

Abstract: DDR2 Mechanical Dimensions DDR2-667 STLS2E02 STLS2F01 Loongson
Contextual Info: STLS2F01 High performance 64-bit superscalar MIPS Loongson 2F: microprocessor Preliminary Data Features • 64-bit superscalar architecture ■ 900 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set

JESD79-2B

Abstract: CR88 DDR2-667 STLS2E02 STLS2F01 1013tdi
Contextual Info: STLS2F02-LP high performance 64-bit superscalar MIPS Loongson 2F microprocessor Preliminary Data Features • 64-bit superscalar architecture ■ 800 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set

JESD97

Abstract: STLS2E02 35x35 bga Loongson
Contextual Info: STLS2E02 Loongson 2E: 700MHz 64-bit superscalar MIPS based microprocessor Data Brief Features • 64 bit superscalar architecture ■ 700MHz clock frequency typical conditions ■ Single/double precision floating-point units ■ New Streaming Multimedia instruction set

JESD79-2B

Abstract: 0x01000202 CR88 DDR2-667 STLS2E02 STLS2F01 Loongson
Contextual Info: STLS2F02-LP high performance 64-bit superscalar MIPS Loongson 2F microprocessor Preliminary Data Features • 64-bit superscalar architecture ■ 800 MHz clock frequency ■ Single/double precision floating-point units ■ New streaming multimedia instruction set