Intel Processors
Abstract: autocorrelation Parallel FIR Filter image processor linear convolution Transforms Least-mean-square adaptive filters viterbi convolution
Text: Intel Performance Library Suite Do you want to boost the performance of your applications by taking advantage of the latest features of Intel® processors? Would you like to make your software really scalable, even though you can’t afford time-consuming assembly-level
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USA/2K/0598/JM,
Intel Processors
autocorrelation
Parallel FIR Filter
image processor
linear convolution
Transforms
Least-mean-square adaptive filters
viterbi convolution
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LTC1010
Abstract: H0S200 HA-5033 LH0033 OPA602 OPA633 OPA633KP
Text: OPA633 High Speed BUFFER AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● WIDE BANDWIDTH: 260MHz HIGH SLEW RATE: 2500V/µs HIGH OUTPUT CURRENT: 100mA LOW OFFSET VOLTAGE: 1.5mV OP AMP CURRENT BOOSTER VIDEO BUFFER LINE DRIVER A/D CONVERTER INPUT BUFFER
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OPA633
260MHz
100mA
HA-5033
LH0033,
LTC1010,
H0S200
OPA633
LTC1010
H0S200
HA-5033
LH0033
OPA602
OPA633KP
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max442 substitution
Abstract: MAX498 4p2t composite to rgb converter ic MAX440 MAX441 MAX442
Text: VIDEO CIRCUITS Application Note 693: Mar 17, 2000 ICs Boost Video Performance New video ICs are making life easier for design engineers by integrating the functions once implemented with discrete components. The new products not only cost less and save space on the PC
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com/an693
max442 substitution
MAX498
4p2t
composite to rgb converter ic
MAX440
MAX441
MAX442
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B17C
Abstract: frequency divider block diagram simple block diagram for digital clock EP1AGX50DF single phase ups block diagram AGX52001-2 8b10b EP1AGX20CF
Text: 1. Arria GX Transceiver Architecture AGX52001-2.0 Introduction Arria GX is a protocol-optimized FPGA family that leverages Altera’s advanced multi-gigabit transceivers. The Arria GX transceiver blocks build on the success of the Stratix II GX family and are optimally
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AGX52001-2
8B/10B
B17C
frequency divider block diagram
simple block diagram for digital clock
EP1AGX50DF
single phase ups block diagram
8b10b
EP1AGX20CF
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siemens s7-300 battery replacement
Abstract: 3RV1421 sitop flexi 6EP1336-3BA00 6EP1334-2AA01 siemens 6ep1334-3ba00 siemens 3rv1021 siemens 6ep1961-3BA20 6ep1331-1sh02 siemens sitop power 40
Text: SITOP WS_Dachschrift_GB 03.11.2005 8:32 Uhr Seite 1 C M Y CM MY CY CMY K Have you developed a taste for SITOP? Are you striving for more? Go for a live experience of reliable power without risk! For information and list of contacts, go to www.siemens.com/sitop
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B17C
Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF
Text: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:
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10G BERT
Abstract: altgx bc 201 transistor match line match sense signal EP4S40G5H40 hd-SDI deserializer LVDS HD-SDI over sdh circuit diagram of rf transmitter and receiver GT 6 N 170 k28 60 pcie Gen2 payload
Text: 1. Stratix IV Transceiver Architecture SIV52001-4.l This chapter provides details about Stratix IV GX and GT transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. f For information about upcoming Stratix IV device features, refer to the Upcoming
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SIV52001-4
10G BERT
altgx
bc 201 transistor match line match sense signal
EP4S40G5H40
hd-SDI deserializer LVDS
HD-SDI over sdh
circuit diagram of rf transmitter and receiver
GT 6 N 170
k28 60
pcie Gen2 payload
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XC3000A
Abstract: XC3100A XC4000 XC5000
Text: Full-Featured Floorplanner Boosts FPGA Performance The new XACTstep, version 6 release contains the industry’s first graphics-based hierarchical floorplanner. Use of XACTFloorplanner can result in dramatic improvement to FPGA performance, allowing designs to run at higher speed, or
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XC4000
SC-381
XC3000A,
XC3100A,
XC4000,
XC5000
XC3000A
XC3100A
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HIV53001-1
Abstract: CAN BUS megafunction
Text: 1. HardCopy IV GX Transceiver Architecture HIV53001-1.0 Introduction This chapter provides details about HardCopy IV transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. HardCopy IV GX devices deliver a very high level of system bandwidth and power
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HIV53001-1
CAN BUS megafunction
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Untitled
Abstract: No abstract text available
Text: AN11100 SSL21101T flexible focus flyback LED driver application Rev. 1.1 — 25 October 2012 Application note Document information Info Content Keywords SSL21101T, LED, flexible LED driver, LED lighting, LED lamp, SMPS, internal power switch, flyback, buck boost, natural PFC capability
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AN11100
SSL21101T
SSL21101T,
2012information.
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matrix display 5x7
Abstract: No abstract text available
Text: PSoC Creator Component Data Sheet Segment LCD LCD_Seg 2.10 Features • 2 to 768 pixels or symbols • 1/3, 1/4 and 1/5 bias supported • 10 to 150 Hz refresh rate • Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias
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16-segment
matrix display 5x7
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet Segment Display Seg_Display 1.10 Features • Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component.) • 2 to 768 pixels or symbols
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150-Hz
16-segment
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet Segment LCD LCD_Seg 3.10 Features • 2 to 768 pixels or symbols • 1/3, 1/4 and 1/5 bias supported 10- to 150-Hz refresh rate Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias
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150-Hz
16-segment
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hd44780 lcd controller Verilog
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet Segment LCD LCD_Seg 3.20 Features • 2 to 768 pixels or symbols • 1/3, 1/4 and 1/5 bias supported 10- to 150-Hz refresh rate Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias
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150-Hz
16-segment
hd44780 lcd controller Verilog
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LCD ascii segment character lookup table source c
Abstract: generic failure rate LCD matrix alphanumeric 14 segment display 16 pin
Text: PSoC Creator Component Datasheet Segment Display Seg_Display 1.20 Features • Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component.) • 2 to 768 pixels or symbols
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150-Hz
16-segment
LCD ascii segment character lookup table source c
generic failure rate LCD matrix
alphanumeric 14 segment display 16 pin
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texas handbook
Abstract: 1008-B
Text: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.
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hd44780 lcd controller Verilog
Abstract: 7-segment digital clock circuit hitachi hd44780
Text: PSoC Creator Component Datasheet Segment LCD LCD_Seg 3.30 Features • 2 to 768 pixels or symbols • 1/3, 1/4 and 1/5 bias supported 10- to 150-Hz refresh rate Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias
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150-Hz
16-segment
hd44780 lcd controller Verilog
7-segment digital clock circuit
hitachi hd44780
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GPON block diagram
Abstract: hd-SDI deserializer LVDS SDI SERIALIZER EP2AGX95EF29 EP2AGX190EF29 SerialLite EP2AGX190 ep2agx65df ENCODER 8 BITS d2151
Text: 1. Arria II GX Transceiver Architecture AIIGX52001-3.0 This chapter describes all the modules that are available in the Arria II GX transceiver architecture and describes how these modules are used in the protocols shown below. In addition, this chapter lists the available test modes, dynamic
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AIIGX52001-3
GPON block diagram
hd-SDI deserializer LVDS
SDI SERIALIZER
EP2AGX95EF29
EP2AGX190EF29
SerialLite
EP2AGX190
ep2agx65df
ENCODER 8 BITS
d2151
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Untitled
Abstract: No abstract text available
Text: AN10831 SSL2102 30 W flyback triac dimmable LED driver Rev. 02 — 23 March 2011 Application note Document information Info Content Keywords SSL2102, LED driver, mains dimmable, triac dimmer, flyback Abstract This application note provides an overview of the considerations when
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AN10831
SSL2102
SSL2102,
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EP2SGX60EF
Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram
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SIIGX52002-4
8B/10B
EP2SGX60EF
CEI 23-16
circuit diagram of PPM transmitter and receiver
CPRI multi rate
HD-SDI over sdh
PRBS10
3G-SDI serializer
k307
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Untitled
Abstract: No abstract text available
Text: B U R R - B R O W N <i [ BUF634 ] 250mA HIGH-SPEED BUFFER FEATURES APPLICATIONS • HIGH OUTPUT CURRENT: 250mA VALVE DRIVER • SLEW RATE: 2000V/|is SOLENOID DRIVER • PIN-SELECTED BANDWIDTH: 30MHz to 180MHz OP AMP CURRENT BOOSTER LINE DRIVER • LOW QUIESCENT CURRENT:
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BUF634
250mA
250mA
30MHz
180MHz
T0-220,
BUF634
17313b5
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Untitled
Abstract: No abstract text available
Text: BURR - BROW N BUF634 AVAILABLE IN DIE 250mA HSGH-SPEED BUFFER FEATURES APPLICATIONS • HIGH OUTPUT CURRENT: 250mA • SLEW RATE: 2000V/|iS VALVE DRIVER SOLENOID DRIVER • PIN-SELECTED BANDWIDTH: 30MHZ/180MHz OP AMP CURRENT BOOSTER LINE DRIVER HEADPHONE DRIVER
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BUF634
250mA
250mA
30MHZ/180MHz
30MHz
T0-220
BUF634
O-220.
5M-1982.
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Untitled
Abstract: No abstract text available
Text: BURR —BROUN 3ME CORP D E 17313bS D D l ò S b 1! 1 E3BUB " P ^ - O b 'l O INÂ117 High Common-Mod Voltage DIFFERENCE AMPLIFIER FEATURES APPLICATIONS O COMWION-MODE INPUT RANGE: ±200V Vs= ±15V O PROTECTED INPUTS: +500V Common-Mode +500V Differential
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17313bS
INA117
17313bS
00162S2
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74LS167
Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
Text: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.
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74LS181
74LS183
74LS190
74LS191
74LS192
74LS193
74LS194A
74LS195A
74S260
74LS261
74LS167
F199 transistor
74LS382
74LS514
74LS76A
transistor b1100
74LS204
74ls171
F199
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