BALTIMORE Search Results

DS2013D

Abstract: DS2009R DS2010 DS2011D DS2015 DS1609 DS2013 "Dual-Port RAM" DS2010R DS2011
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244–3292 214 450–0400 Date: September 20, 1996 To: MET Laboratories, Baltimore, MD Subject: PRODUCT CHANGE NOTICE – H62901 Description: Product Obsolescence – DS20XX FIFO Family and

NONLINEAR MODEL LDMOS

Contextual Info: Slide 1 Extracting RF Mosfet Spice Models MTT 1998 - Baltimore Md. by S. K. Leong Polyfet Rf Devices www.polyfet.com This presentation is available on our web site Slide 2 Why simulate? n n n n n n n Simulation - It’s the only way! Fast accurate results. What if analysis.

scta032

Contextual Info: A Proposed Method of Accessing 1149.1 in a Backplane Environment Lee Whetsel SCTA032 Reprinted with permission from Proceedings of International Test Conference, Baltimore, Maryland, September 20–24, 1992.  1992 IEEE 1 2 3 4 5 6 7 8 9 10 11 12 13 IMPORTANT NOTICE

Contextual Info: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993. SCTA033

conference system

Abstract: semiconductor
Contextual Info: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated Senior Member Technical Staff Semiconductor Group SCTA033  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993.

semiconductor

Abstract: SEMICONDUCTOR DATA BOOK Seniors
Contextual Info: A Proposed Method of Accessing 1149.1 in a Backplane Environment Lee Whetsel Senior Member Technical Staff Semiconductor Group SCTA032 Reprinted with permission from Proceedings of International Test Conference, Baltimore, Maryland, September 20–24, 1992.

fiber optics

Contextual Info: Infineon Technologies AG - Infineon Technologies AG - Fairs Seite 1 von 2 Infineon Homepage Fiber Optics Please Select A Topic Products - Fiber Optics Trade Show Schedule Trade Show OFC 2000 Date March 7 - 9, 2000 Location Baltimore Convention Center Baltimore, Maryland, USA

bias for position detector udt

Abstract: pin-SPOT-4D LSC-30D PINSPOT2D SPOT-4D UDT BNC PINSC10D PINLSC30D SC-10D PIN-SPOT
Contextual Info: MODEL 301DIV SIGNAL CONDITIONING AMPLIFIER 727 South Wolfe Street Baltimore, Maryland 21231 Phone: 410.342.2626 Fax: 410.342.7028 Website: www.udtinstruments.com Rev B July 20, 2005 Dear Valued Customer: The conventional fuse in your Model 301-DIV has been replaced with a self-resetting fuse. This new “fuse” is actually a

Contextual Info: A Proposed Method of Accessing 1149.1 in a Backplane Environment Lee Whetsel SCTA032 Reprinted with permission from Proceedings of International Test Conference, Baltimore, Maryland, September 20–24, 1992.  1992 IEEE 1 3 4 5 6 7 8 9 10 11 12 13 IMPORTANT NOTICE

TMS320C64X disparity

Abstract: led research paper lcd navy stereoscopic sync HA-5033 scheme tv color 230Mpixels C67x
Contextual Info: Status and Hardware Requirements of 3D Imaging Systems ∗♠ Charles Johnson-Bey, ♣ Otsebele Nare, ♣Craig Scott Morgan State University School of Electrical and Computer Engineering 5200 Perring Parkway, Baltimore, MD 21251, USA ABSTRACT The real world is composed of objects in three

scta033

Contextual Info: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993. SCTA033

25275

Contextual Info: TE X A S IN S T R { L I N / I N T F O T s D Ê| 0033=127 TELECOM CIRCUITS r 3 T-75-11-37 TCM2101/2 PCM REPEATER DECEMBER 1982 Features GND M • • • • • • • PCM Signal amplification Two ALBO taps High Q or Low Q clock extraction Decision time adjustment

ande RY 192

Abstract: ande RY 228 ande RY 227 mov rdn 240 DB14-000121-00
Contextual Info: LSI402Z Digital Signal Processor User’s Guide May 2000 Order Number R14014 LSI Logic Confidential This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties

sem 2105

Abstract: UA 7300 EPC D3318 LSI53C875 LSI53C875A PC99 UC5601QP S14047 B4128 30345
Contextual Info: TECHNICAL MANUAL LSI53C875A PCI to Ultra SCSI Controller Version 2.0 December 2000 S14047 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

LSI53C896

Abstract: ami 2109 el 7406 LSI53C876 PAR64 ADB 424 D3318
Contextual Info: TECHNICAL MANUAL LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller Version 3.2 April 2001 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties

LSI53C141

Abstract: D3318 LSI53C120 LSI53C876 LSI53C895 SD12 SD14
Contextual Info: TECHNICAL MANUAL LSI53C141 SCSI Bus Expander Version 2.1 November 2000 S14013.A This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

Db06

Abstract: mov rdn 240 elektronik DDR D3318 haar transform
Contextual Info: User’s Guide LSI402ZX Digital Signal Processor Preliminary March 2001 R14021.B This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

mk48t18

Abstract: LSI53C1510 LSI53C895 LSI53C896 alaska ultra reference design schematics 20405 MFA D3318
Contextual Info: TECHNICAL MANUAL LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller Version 2.2 April 2001 S14024.B This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties

E1110

Abstract: structure of GMII packet with VLAN Tag E1110 S 20 diode E1110 mac 226 E-1110 TXSV37 E110.000
Contextual Info: TECHNICAL MANUAL E-1110 10/100/1000 Mbits/s Ethernet MAC Preliminary April 2001 R14024 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

diagram of bp 1361 led driver

Abstract: LSIFC909 DB14-000150-01 M66EN PAR64 PC99 D3318
Contextual Info: LSIFC909 Fibre Channel I/O Processor Technical Manual August 2000 Version 2.1 Order Number S14029.A This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties

flip-flop 948

Abstract: 5252 f 1101 SN74AS8840 CNTR11-CNTR8 Zeus Component AS8832
Contextual Info: SN74AS8840. Digital Crossbar Switch • High-speed programmable switch for parallel processing applications • Dynam ically reconfigurable for fault-tolerant routing • 64 bidirectional data I/O s in 16 nibble four-bit groups • D ata I/O selection programmable by nibble

TMS320VC541

Abstract: S320VC TMS320VC542
Contextual Info: TMS320C54X, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS S P R S 039- FEBRUARY 1996 • 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators • 17- x 17-Bit Parallel Multiplier Coupled to a

Contextual Info: SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS131-AUGUST 1992-REVISED OCTOBER 1992 • SCOPE Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1 A CLAMP and HIGHZ - Parallel Signature Analysis at Inputs With

Contextual Info: PRELIMINARY BEYOND PERFORMANCE VANTI S VF1 FIELD PROGRAMMABLE GATE ARRAY FEATURES AND BENEFITS ♦ The industry's first Variable-Grain-Architecture enables high-density, high-performance designs for a wide range of applications — Architecture adapts to logic to enable synthesis-friendly, high-performance designs