B13 TRANSITOR Search Results

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Catalog Datasheet	MFG & Type	Document Tags	PDF
UPD 552 C Abstract: LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 Text: XC5200 Field Programmable Gate Arrays  June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	Original	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 UPD 552 C LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210	PDF
LC1 D12 P7 Abstract: XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 XC5215 Text: XC5200 Field Programmable Gate Arrays  August 6, 1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	Original	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 XC5215	PDF
320C50A Abstract: C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 RW109 C50A-50 Text: SMJ320C50A DIGITAL SIGNAL PROCESSOR SGUS018 – JANUARY 1994 • • • • • • • • • • • • • • • • • 100 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1 99 ÉÉÉ ÉÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ 33 66 • ÉÉ ÉÉ ÉÉÉ ÉÉÉ HFG PACKAGE	Original	SMJ320C50A SGUS018 MIL-STD-883, 16-Bit 32-Bit 320C50A C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 RW109 C50A-50	PDF
datasheet ci 4011 Abstract: C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 Text: SMJ320C50A DIGITAL SIGNAL PROCESSOR SGUS018 – JANUARY 1994 • • • • • • • • • • • • • • • • • 100 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1 99 ÉÉÉ ÉÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ 33 66 • ÉÉ ÉÉ ÉÉÉ ÉÉÉ HFG PACKAGE	Original	SMJ320C50A SGUS018 MIL-STD-883, 16-Bit 32-Bit datasheet ci 4011 C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50	PDF
Untitled Abstract: No abstract text available Text: SM320C50-EP DIGITAL SIGNAL PROCESSOR SGUS040 – AUGUST 2002 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product Change Notification Qualification Pedigree†	Original	SM320C50-EP SGUS040 TMS320C1x TMS320C2x 16-Bit 32-Bit	PDF
TMS320LC549 Abstract: TMS320LC549GGU TMS320VC549 Text: TMS320LC549 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU	Original	TMS320LC549 SPRS077B 16-Bit 40-Bit 17-Bit TMS320LC549 TMS320LC549GGU TMS320VC549	PDF
TMS320VC549 Abstract: SPRS078F Text: TMS320VC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU	Original	TMS320VC549 SPRS078F 16-Bit 40-Bit 17-Bit TMS320VC549 SPRS078F	PDF
TMS320LC548 Abstract: TMS320LC548GGU BDX0 Text: TMS320LC548 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS123 – FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two	Original	TMS320LC548 SPRS123 16-Bit 40-Bit 17-Bit TMS320LC548 TMS320LC548GGU BDX0	PDF
BDX 241 Abstract: bdx 530 TMS320VC549 tms 3899 Non-Pipelined Single-Cycle processor BDR-1 Text: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS078E – SEPTEMBER 1998 – REVISED JANUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU	Original	SPRS078E 16-Bit 40-Bit 17-Bit BDX 241 bdx 530 TMS320VC549 tms 3899 Non-Pipelined Single-Cycle processor BDR-1	PDF
Untitled Abstract: No abstract text available Text: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	Original	XC5200 dedicated24 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240	PDF
X9009 Abstract: r13-112 switch XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 X-9009 XC5215 Text: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	Original	XC5200 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 X9009 r13-112 switch XC3000 XC4000 XC5202 XC5204 XC5206 X-9009 XC5215	PDF
Untitled Abstract: No abstract text available Text: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU	Original	SPRS077B 16-Bit 40-Bit 17-Bit	PDF
LC1 D18 wiring diagram Abstract: 8165 input chip chart XC520 XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 XC3000 Text: Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology	Original	XC5200 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 LC1 D18 wiring diagram 8165 input chip chart XC520 XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 XC3000	PDF
AS 108-120 Abstract: LC1 D12 10 LC1 D18 wiring diagram X4963 LC1 D12 P7 XC3000 XC4000 XC5200 XAPP 017 XC5204 Text: 1 1 XC5200 Series Field Programmable Gate Arrays  December 10, 1997 Version 5.0 1 4* Features Product Specification • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology	Original	XC5200 XC5202 XC5204 XC5206 XC5210 XC5215 PQ100 VQ100 TQ144 PG156 AS 108-120 LC1 D12 10 LC1 D18 wiring diagram X4963 LC1 D12 P7 XC3000 XC4000 XAPP 017 XC5204	PDF

Untitled Abstract: No abstract text available Text: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support	Original	SM320C50EP SGUS040A TMS320C1x TMS320C2x 16-Bit	PDF
Untitled Abstract: No abstract text available Text: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support	Original	SM320C50EP SGUS040A TMS320C1x TMS320C2x 16-Bit	PDF
SMJ320C50 Abstract: SMJ320C50GFAM50 SMJ320C50GFAM66 SMJ320C50HFGM50 SMJ320C50HFGM66 SMQ320C50PQM66 Text: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 D D D D D D D D D D D D D D D D D ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 100 ÉÉ ÉÉ ÉÉ ÉÉ 1 99 33 66 D HFG PACKAGE TOP VIEW 132 D D Military Operating Temperature Range:	Original	SMJ320C50/SMQ320C50 SGUS020 MIL-PRF-38535 16-Bit 32-Bit SMJ320C50 SMJ320C50GFAM50 SMJ320C50GFAM66 SMJ320C50HFGM50 SMJ320C50HFGM66 SMQ320C50PQM66	PDF
Untitled Abstract: No abstract text available Text: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support	Original	SM320C50EP SGUS040A TMS320C1x TMS320C2x 16-Bit	PDF
Untitled Abstract: No abstract text available Text: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support	Original	SM320C50EP SGUS040A TMS320C1x TMS320C2x 16-Bit	PDF
Untitled Abstract: No abstract text available Text: £ XC5200 Field Programmable Gate Arrays x ilin x August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 PQ100 VQ100 TQ144 PG156 XC5202 XC5204 XC5210 XC5215 PQ160	PDF
Untitled Abstract: No abstract text available Text: JIXILINX XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 XC5202 XC5204 XC5206	PDF
ATIC 164 D2 44 pin Abstract: ATIC 164 D2 48 pin ATIC 164 D3 Text: H X IL IN X XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Prelim inary Product Specification Features • • High-density family of Field-Program m able Gate Arrays (FPGAs) • Design- and process-optimized for low cost - 0.6-nm three-layer metal (TLM) process	OCR Scan	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 ATIC 164 D2 44 pin ATIC 164 D2 48 pin ATIC 164 D3	PDF
GV1 M10 Abstract: TPC842 A7 B14 Text: tlX IU N X XC5200 Field Programmable Gate Arrays August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 -403C XC5202 XC5204 XC5206 XC5210 XC5215 PQ100 VQ100 TQ144 GV1 M10 TPC842 A7 B14	PDF
gc 7137 ad Abstract: transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin Text: £ XILINX XC5200 Series Field Programmable Gate Arrays Novem ber 5, 1998 Version 5.2 Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogram m able architecture - 0.5\|j.m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	OCR Scan	XC5200 distribution156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 gc 7137 ad transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin	PDF

B13 TRANSITOR Search Results

B13 TRANSITOR Datasheets Context Search

UPD 552 C

LC1 D12 P7

320C50A

datasheet ci 4011

Untitled

TMS320LC549

TMS320VC549

TMS320LC548

BDX 241

Untitled

X9009

Untitled

LC1 D18 wiring diagram

AS 108-120

Untitled

Untitled

SMJ320C50

Untitled

Untitled

Untitled

Untitled

ATIC 164 D2 44 pin

GV1 M10

gc 7137 ad