B 9 LAT Search Results

74ABT899

Abstract: 74ABT899CMSA 74ABT899CQC 74ABT899CSC M28B MO-047 MS-013 MSA28 V28A
Contextual Info: . R e v is e d J a n u a ry 1 9 9 9 S E M i C O N D U C T O R TM 74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description • A b ility to s im u lta n e o u s ly g e n e ra te a n d c h e c k p a rity T h e A B T 8 9 9 is a 9 -b it to 9 -b it p a rity tra n s c e iv e r w ith tra n s ­

F-95972

Contextual Info: Ille Rechte Vorbehalten/ HU rigkts ris a n i P r i n t e d Board Layout component s id e 2 6 , 61 2 x M2,5 No. 1 c o n t a c t 2 3 , 61 \ qj UUUUUUUTTO UUUUUUUTT B9 E 3 B 9 E 3 B 9 E 3 B 9 E 3 B 9 E 3 B 9 E 3 B 9 E 3 B 9 E 3 B9 C O BBPBPBaHaHBHaBBBBB IO v n n n n n n r m n n n n n n n nnn7

Contextual Info: BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV Standard ICs 12-bit, serial IN, parallel OUT driver BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV T h e B U 2 0 9 0 , B U 2 0 9 0 F , B U 2 0 9 0 F S , B U 2 0 9 2 , B U 2 0 9 2 F , a nd B U 2 0 9 2 F V a re 1 2 -b it s e ria l in p u t, p a ra lle l o u tp u t

MC14599

Abstract: 14599b MC14599B
Contextual Info: MOTOROLA MC14099B MC14599B 8-B IT ADDRESSABLE LATCHES Th e M C 1 4 0 9 9 B and M C 1 4 5 9 9 B are 8 b it addressable latches. Data is entered in serial fo rm w h en the a p p ro p ria te la tc h is addressed via address pins AO, A t , A2> and w rite disable is in th e lo w state.

Contextual Info: MEMORY 5V-0NLY FLASH MEMORY CARD M B 9 8 A 8 1 0 6 3 -1 5 /M B 9 8 A 8 1 1 8 3 -1 5 /M B 9 8 A 8 1 2 7 3 -1 5 / M B 9 8 A 8 1 3 7 3 -1 5 /M B 9 8 A 8 1 4 7 3 -1 5 /M B 9 8 A 8 1 5 7 3 -1 5 1M /2M /4M /8M /16M /32M -BYTE 5V-ONLY FLASH ERASABLE AND PROGRAM M ABLE MEMORY CARD

CHIPX

Abstract: MB98A81183-15 mb98a800 H-38-H
Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-30333-3E MEMORY 5V-ONLY FLASH MEMORY CARD M B 9 8 A 8 1 0 6 3 -1 5 /M B 9 8 A 8 1 1 8 3 -1 5 /M B 9 8 A 8 1 2 7 3 -1 5 / M B 9 8 A 8 1 3 7 3 -1 5 /M B 9 8 A 8 1 4 7 3 -1 5 /M B 9 8 A 8 1 5 7 3 -1 5 1M/2M/4M/8M/16M/32M-BYTE 5V-ONLY

m36a

Contextual Info: T M 4 9 7 M B M 3 6 A , T M 4 9 7 M B M 3 6 Q 41 9 4 3 0 4 BY 36-BIT T M 8 9 3 N B M 3 6 A , T M 8 9 3 N B M 3 6 Q 8 3 8 8 6 0 8 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B - MAY 1995 - REVISED JULY 1995 O r ga ni z a t i on T M4 9 7 M B M 3 6 A . . . 41 9 4304 x 36

MC14106

Abstract: MC14599BCP MC14099B MC14599BCL 4599B CD4099B MC14 MC14094B MC14099BCL mc14094
Contextual Info: MC14094B BLOCK DIAG RAM Register Stag« 1 Latch 1 6-173 3 Stata B uffar 1 MC14097B See Page 150 M O T O R O L A MC14099B MC14599B 8-BIT ADDRESSABLE LATCHES The M C 1 4 0 9 9 B and M C 1 4 5 9 9 B are 8 -b it addressable fatches. D a ta is entered in serial fo rm w h en th e a p p ro p ria te la tc h is addressed

Contextual Info: DATEREV1 V NÇ ANDRISK P08ITR0NICASSUMES MORESPONSIBILITYFOR RESULTSOBTAINEDORDAMAGESINCURREDFROMUSEOF SUCHINFORMATIONINWHOLEORINPART. 8111821 REVISIONRECORD ECO 33281 lAPPlDRlCKl SEE! EE P B I B B B are I B •0.583 [ 1 4 . 8 1 ]- - - - - - - - - - - - - 1 .2 2 0 [3 0 .9 9 ].

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9 -B it Latch ECL/TTL Translator M C10H603 M C 100H 603 The M C 10H /100H 603 is a 9 -b it, dual supp ly ECL to T T L translator. Devices in the M otorola 9 -b it tra n sla tor series utilize th e 2 8 -le a d PLCC for

74HC4543

Abstract: pin diagram of ic 40098 74HCt4543
Contextual Info: Technical Data CD54/74HC4543 CD54/74HCT4543 File Number 1822 High-Speed CMOS Logic BCD INPUTS 7 - SEGMENT OUTPUTS .9 L_~0N “ b 11 —c 13 BCD-to-7 Segment Latch/ Decoder/Driver for LCDs a i s 3 5 b 7B«Ï 7 03- 8 9 B 9 2 C S - 23087 LD •— GND» 8 Vcc*!6

74ACT899

Abstract: 74ACT899QC MO-047 V28A
Contextual Info: T S H c I L D J a n u a ry 1990 R e v is e d D e c e m b e r 199 8 S E M IC O N D U C T O R TM 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description Features T h e A C T 8 9 9 is a 9 -b it to 9 -b it p a rity tra n s c e iv e r w ith tra n s ­

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-20685-3E FLASH MEMORY B lB 2M 256K X 8/128K x 16 BIT M B M 2 9 L V 2 0 0 T C -7 0 -M 1 2 /M B M 2 9 L V 2 0 0 B C -7 0 -9 0 -1 2

Contextual Info: TC4099BIVBF C 2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4099BP/TC4099BF 8-BIT ADDRESSABLE LATCH TC40 9 9 B P / B F is eight bit l atch having one common data input line and eight independent output lines and the l a t ches are controlled b y three bit b i n a r y address

LVT16244A

Abstract: SN54LVT16244A SN74LVT16244 SN74LVT16244A
Contextual Info: SN54LVT16244A, SN74LVT16244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS S C B S 1 4 2 B - M A Y 1 9 9 2 - R E V IS E D F E B R U A R Y 1 9 9 4 SN54LVT16244A . . . WD PACKAGE SN74LVT16244 . DGG OR DL PACKAGE TOP VIEW State-of-the-Art Advanced BiCMOS

14599B

Abstract: MC14099B-MC14599B MC14599BCP MC14599BCL
Contextual Info: MC14097B See Page 150 M O TO R O LA M C14099B M C14599B 8-BIT ADDRESSABLE LATCHES The M C 1 4 0 9 9 B and M C 1 4 6 9 9 B are 8 b it addressable latches. Data is e ntered in serial fo rm w h en th e a p p ro p ria te la tc h is addressed {via address pins AO. A 1 . A 2 and w r ite disable is in th e lo w state.

mitsubishi ecu

Contextual Info: blE MITSUBISHI LSIs M5M5179AP, J, FP-15, -20,-25 7 3 7 2 8 -B IT 8 1 9 2 -W O R D BY 9 -B IT C M 0 S STATIC RAM MI T S U B I S H I (M E M O R Y / A S I C ) DESCRIPTION This is a fa m ily o f 8 1 9 2 w o rd b y 9 -b it static R A M s , fa b r i­ PIN CONFIGURATION (TOP VIEW)

Contextual Info: MITSUBISHI LSIs M5M5179AP,J,FP-20,-25 7 3 7 2 8 -B IT 8 1 9 2 -W O R D BY 9 -B IT C M 0 S STATIC RAM DESCRIPTION This is a fa m ily o f 8 1 9 2 word by 9-b it static R A M s , fa b ri­ PIN CONFIGURATION (TOP VIEW) cated w ith the high performance C M OS silicon gate MOS

MBM29LV200B

Contextual Info: FLASH MEMORY B l I l i 2M 256K x 8/128K x 16 BIT M B M 2 9 L V 2 0 0 T - 12- x / M B M 2 9 L V 2 0 0 B - 12- x

100k series ecl

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9 -B it Latch TTL/ECL Translator M C 10H 602 M C 100H 602 The MC10H/100H602 is a 9-bit, dual supply TTL to ECL translator with latch. Devices in the Motorola 9 -b it translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical

Contextual Info: D S 9 9 R 1 0 5 ,D S 9 9 R 1 0 6 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Texas INSTRUMENTS Literature Number: SNLS242C £/r Semiconductor D S 9 9 R 1 0 5 /D S 9 9 R 1 06 3 -4 0M H z D C -B alanced 2 4-B it LVD S S e ria lize r and

Contextual Info: TYPES SN54LS594, SN54LS599, SN74LS594, SN74LS599 8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES D 2747, JU N E 1983 - 8-B it Serial-ln, Parallel-Out Shift Registers w ith Storage R E V IS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 5 9 4 . S N 5 4 L S 5 9 9 . . . J OR W PACKAGE

5890A

Abstract: UCN5891A ucn5891b
Contextual Info: UCN-5890A/B AND UCN-5891A/B BiMOS II 8-BIT, SERIAL-INPUT, LATCHED SOURCE DRIVERS U C N -58 9 0A /B A N D U CN -58 9 1A /B B iM O S II 8-BIT, SER IA L-IN PU T, LATCHED SO U RCE DRIVERS FEATURES • • • • • 50 V or 80 V Source O utputs Output Current to - 500 mA

Contextual Info: MITSUBISHI LSIs M5M5179P-35, -45, -55 7 3 7 2 8 -B IT 8 1 9 2 -WORD BY 9 -B IT C M 0 S STATIC RAM DESCRIPTION This is a fam ily o f 8 1 9 2 word by 9 -b it static RAM s, fabri­ PIN CONFIGURATION (TOP VIEW) cated w ith the high performance CMOS silicon gate MOS