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    Nexperia 74AHC00PW-Q100J

    Logic Gates 74AHC00PW-Q100/SOT402/TSSOP14
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    TTI 74AHC00PW-Q100J Reel 10,000 2,500
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    Nexperia 74HCT2G08DP-Q100H

    Logic Gates 74HCT2G08DP-Q100/SOT505/TSSOP8
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    TTI 74HCT2G08DP-Q100H Reel 6,000
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    ANDGATE Datasheets Context Search

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    rneg2

    Abstract: No abstract text available
    Text: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data


    Original     		PDF TXC-03103C TXC-03103C-MB, rneg2

    Untitled

    Abstract: No abstract text available
    Text: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV164A, SN74LV164A SCLS403D 000-V A114-A) A115-A) SN54LV164A SN74LV164A

    A115-A

    Abstract: C101 SN54LV164A SN74LV164A
    Text: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV164A, SN74LV164A SCLS403D SN54LV164A 000-V A114-A) A115-A) A115-A C101 SN54LV164A SN74LV164A

    Untitled

    Abstract: No abstract text available
    Text: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003 D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 20 ns


    Original     		PDF SN54HC164, SN74HC164 SCLS115D SN54HC164

    LV164A

    Abstract: A115-A C101 SN54LV164A SN74LV164A
    Text: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF


    Original     		PDF SN54LV164A, SN74LV164A SCLS403G SN54LV164A LV164A A115-A C101 SN54LV164A SN74LV164A

    integrated circuit sn74hc164n diagram

    Abstract: SN74HC164N
    Text: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D D D SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D, N, NS, OR PW PACKAGE TOP VIEW Wide Operating Voltage Range of 2 V to 6 V


    Original     		PDF SN54HC164, SN74HC164 SCLS115C SN54HC164 SN74HC164 SN74HC164N3 SN74HC164NSR SN74HC164PW SN74HC164PWR integrated circuit sn74hc164n diagram SN74HC164N

    set top box video recorder

    Abstract: No abstract text available
    Text: TSB42AA4/42AA4I TSB42AB4/42AB4I ceLynx IEEE 1394.a Consumer Electronics Link Layer Controller Data Manual April 2003 Mixed Signal Products SLLS341E IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,


    Original     		PDF TSB42AA4/42AA4I TSB42AB4/42AB4I SLLS341E 4087726/A S-PQFP-G144) MS-026 set top box video recorder

    TMS320C5000

    Abstract: XDS100 TMS320C5514
    Text: TMS320C5514 SPRS646D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5514 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5514 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor


    Original     		PDF TMS320C5514 SPRS646D TMS320C5514 TMS320C55xTM 33-ns 120-MHz TMS320C5000 XDS100

    Untitled

    Abstract: No abstract text available
    Text: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80- A Max ICC Typical tpd = 20 ns


    Original     		PDF SN54HC164, SN74HC164 SCLS115E SN54HC164 SN74HC164

    Untitled

    Abstract: No abstract text available
    Text: TMS320C5515 SPRS645D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor


    Original     		PDF TMS320C5515 SPRS645D TMS320C5515 10-Bit

    SN7470

    Abstract: No abstract text available
    Text: SN5470, SN7470 AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR SDLS116 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments


    Original     		PDF SN5470, SN7470 SDLS116 SN7470

    Untitled

    Abstract: No abstract text available
    Text: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE


    Original     		PDF SN54LV164A, SN74LV164A SCLS403H 000-V A114-A) A115-A) SN54LV164A SN74LV164A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK


    Original     		PDF SN54LV164A, SN74LV164A SCLS403H 000-V A114-A) A115-A) SN54LV164A SN74LV164A

    Untitled

    Abstract: No abstract text available
    Text: TMS320C5515 www.ti.com SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013 TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor


    Original     		PDF TMS320C5515 SPRS645F TMS320C5515 TMS320C55xâ 33-ns 120-MHz

    plhs18p8

    Abstract: PLHS18 PLHS18P8A
    Text: Signetics Military Standard Products PLHS18P8A Programmable AND Array Logic 18x72x8 Product Specification PIN CONFIGURATION DESCRIPTION FE A TU R E S The PLHS18P8A is a two-level logic ele­ ment consisting of 72 ANDgates and SOR gates with fusible connections for pro­


    OCR Scan     		PDF PLHS18P8A PLHS18P8A 18x72x8) plhs18p8 PLHS18

    DD 127 D TRANSISTOR

    Abstract: No abstract text available
    Text: rZ 7 S G S -T H O M S O N Ë [RfflD g[E [l[LI Tri®K]D©i HCC/HCF4068B 8-INPUT NAND/ANDGATE . MEDIUM-SPEED OPERATION - tpHL tpm = 75ns (typ. AT 10V • BUFFERED OUTPUT . QUIESCENT CURRENT SPECIHED TO 20V FOR HCC DEVICE . 5V, 10V, AND 15V PARAMETRIC RATINGS


    OCR Scan     		PDF HCC/HCF4068B 100nA HCC4066BF HCF4068BM1 HCF4068BEY HCF4068BC1 HCC4068B Dbb463 PLCC20 DD 127 D TRANSISTOR

    MH 7472

    Abstract: ic 7472 ttl 7472 ttl TTL 7472
    Text: SN5472, SN7472 AND-GATED J-K M ASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1963 - REVISED MARCH 1988 S N 5 4 7 2 . . J P AC KA G E S N 7 4 7 2 . . . N P AC K A G E Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages TO P VIE W


    OCR Scan     		PDF SN5472, SN7472 MH 7472 ic 7472 ttl 7472 ttl TTL 7472

    SN54L71

    Abstract: No abstract text available
    Text: TYPESN54L71 AND-GATED R-S MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR ' D e p e n d a b le T exas In s tru m e n ts Q u a lity and R e lia b ility REVISED DECEMBER 1983 S N 5 4 L 7 1 . . . J P AC K A G E {TO P V IE W NCC 1 CLRC 2 S1C 3 S2C 4 Ü 1 4 D vcc


    OCR Scan     		PDF TYPESN54L71 SN54L71 SN54L71

    PAL16H8

    Abstract: 16H8 8103614RX AmPAL16
    Text: AmPAL*16XX Family 20-Pin IMOX Programmable Array Logic PAL Elements PRELOAD feature permits full logical verification Reliability assured through more than 70 billion fuse hours of life testing with no failures Full AC and DC parametric testing at the factory through


    OCR Scan     		PDF 20-Pin PAL16H8 16H8 8103614RX AmPAL16

    ampal16r8l

    Abstract: 16H8 AMPAL16R4L AMPAL16L8A/BSA AmPAL16L8L
    Text: AmPAL16R8 Fam ily 20-Pin IMOX Programmable Array Logic PAL Elements Distinctive Characteristics • AMD's superior IMOX technology - Guarantees tpo = 15 ns Max. "B " Versions • High-Speed, Half-Power ("A L") and Quarter-Power ("Q ") versions • Platinum-silicide fuses and added test words ensure


    OCR Scan     		PDF AmPAL16R8 20-Pin KS000010 L16R8 ampal16r8l 16H8 AMPAL16R4L AMPAL16L8A/BSA AmPAL16L8L

    SN74HC104

    Abstract: 54HC164
    Text: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SH IR REGISTERS SCLS115A - DECEM BER 1982 - REVISED JANUARY 1996 AND-Gated Enable/Disable Serial Inputs • • SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D OR N PACKAGE (TOP VIEW) Fully Buffered Clock and Serial Inputs


    OCR Scan     		PDF SN54HC164, SN74HC164 SCLS115A 300-mll SN54HC164 SN74HC164 SN74HC104 54HC164

    Untitled

    Abstract: No abstract text available
    Text: 8-BIT SN74ALS164 PARALLEL-OUT SERIAL SHIFT REGISTERS D2M1. APRIL 1982 - REVISED JANUARY 1989 AND-Gated Enable/Citable Serial Input* S N 7 4 A L 8 W 4 . . . D OR N PACKAGE (TO P V IE W ) Fully Buffered Clock and Serial Input* Direct Clear Package Option* Include Plaatlc "Smalt


    OCR Scan     		PDF SN74ALS164 300-mll N74ALS164

    16H8

    Abstract: AMD 16L8 AMPAL16H8 16a8 AmPAL16R6 AMPAL16L8/BRA AmPAL16R8 16LD8 TFK S 417 T pAL programming Guide
    Text: AmPAL*16XX Family 20-Pin IMOX Programmable Array Logic PAL Elements PRELOAD feature perm its full logical verification Reliability assured through m ore than 70 billion fuse hours o f life testing w ith no failures Full AC and DC param etric testing at the factory through


    OCR Scan     		PDF 20-Pin PF000380 16H8 AMD 16L8 AMPAL16H8 16a8 AmPAL16R6 AMPAL16L8/BRA AmPAL16R8 16LD8 TFK S 417 T pAL programming Guide

    SN7472

    Abstract: SN54110 SN74 SN74110
    Text: TYPES SN54110, SN74110 AND-GATED J -K MASTER-SLAVE FLIP-FLOPS WITH DATA LOCKOUT REVISED DECEMBER 1983 P a cka g e O p tio n s In c lu d e P la s tic and C e ra m ic DIPs S N 5 4 1 10 . . . J OR W PACKAG E S N 7 4 1 10 . . . J O R N PACKAGE T O P V IE W


    OCR Scan     		PDF SN54110, SN74110 SN54110 SN74110 25-MHz SN7472 SN74