AGERE C8 Search Results

BROADCOM AC131

Abstract: 88e6021 88E6218 ADM6609 BCM5241
Contextual Info: IC MANUFACTURER VS PREMIER MAGNETICS IC Manufacturer IC Part Number 1x1 RJ45 RJ45/USB Agere ET901 ET908 RJ3-69ND2 RJ45-103CGYDA2 RJ44-1012DYD2 AMD AM79C874/C875 AM79C971/C972/C973 AM79C975/C976/C977 RJ3-69ND2 RJ45-103CGYDA2 RJ44-1012DYD2 RJ3-69ND2 RJ45-103CGYDA2

TADM04622

Abstract: TDAT04622 TMXF28155 TSI-16 TSWC01622 TSWC03622 f2021
Contextual Info: a'e re AdLib OCR Evaluation systems Preliminary Data Sheet May 2002 TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description . Same functionality as TSWC01622 with reduced jitter specifications The Agere Systems TSWC03622 is designed for a

rtl8211

Abstract: 88e6095 RTL8150 ADM6609 88E6063 88E6218 BCM5350 88E6060 88E6052 88e6083
Contextual Info: IC Cross Reference Magnetic Integrated Connector Modules 1000Base-T Applications E & E Magnetic Products Limited 1000BASE-T APPLICATIONS IC Information Manufacturer Agere Broadcom Part Number Cross Reference Package Type Footprint Style E&E Part Number Data Sheet

16411A1

Abstract: MARKING CODE ADEE ED9 marking diode Marking a4v DSP16000 marking code A6V DSP16410 DSP16411 TDO01 DSP16K
Contextual Info: Advisory December 2002 DSP16411 SEMI Design Exception Overview Agere Systems’ DSP16411 is the next-generation digital signal processor based on the DSP16000 core architecture offering increased speed and on-chip memory. The system and external memory interface

STSI-144

Contextual Info: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

fiber-optic link receiver

Abstract: 700B MAX1771 STM-16 1320PT for APD bias digital microammeter
Contextual Info: Application Note December 1998 Interfacing and Biasing the 1320-Type 2.5 Gbits/s Fiber-Optic Receiver Introduction Proper use of the Agere Systems Inc. 1320-Type 2488.320 MHz fiber-optic receiver, along with recommended circuit connections, is essential to optimum

RXD55

Abstract: RXD26
Contextual Info: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

Contextual Info: Hardware Design Guide May 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

TS127 08

Abstract: RXD55 ts50 STSI-144
Contextual Info: Advance Information June 2003 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

TXD52

Abstract: Agere L-327HB-DT AF10 AC24
Contextual Info: Hardware Design Guide June 2004 STSI-48 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-48 device. Information relevant to the use of

Contextual Info: Hardware Design Guide November 2004 STSI-48 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-48 device. Information relevant to the use of

TL 2272 DECODER

Abstract: 30014 TL 2262 tl 2262 am TL 2272 LU6X14FT Synopsys 2262 encoder l31c ORT82G5
Contextual Info: Preliminary Data Sheet July 2001 ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC Introduction Agere Systems Inc. has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable

47AB

Abstract: SCD1U16V3KX BCB25 BC536 BC163 216t9 sis645dx foxconn WISTRON BC466
Contextual Info: CLK GEN TOUCAN2 DesKtop-CPU Northwood 2.2~3.06GHz ICS:ICS952004AG DDRBUF:ICS93732 3,4 5,6 VRAM*2 FSB 533/400MHz K4D263238M-QC40 CRT 17 2.5V 200MHz/266MHz DDR * 2 11,12,13 SiS962 24 CD-ROM AGP 4X W/RTC 15" MII LAN MAC PHY 20,21,22,23 1394 conn. Agere FW802A

Rxd07

Abstract: ds02123swch
Contextual Info: Advance Information May 2003 TSI-8 Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. TSI-8 device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics,

IC 7411 DATA SHEET

Abstract: z035 DE Z042 0x83CC 4/Z0 607 MA GP 652 Z010 TADM04622 AE Z027 741 IC data sheet z02d
Contextual Info: Data Sheet August 18, 2004 MARS 2G5 P-Pro TDAT162G52 SONET/SDH 155/622/2488 Mbits/s Data Interface Features • ■ ■ ■ One of the next-generation, system-on-a-chip devices of Agere Systems’ multiservice access & rate solutions MARSTM family of framers.

SC100

Abstract: SC140
Contextual Info: MNSC140CORE/D Rev. 3, 11/2001 SC140 DSP Core Reference Manual MNSC140CORE/D Rev. 3, 11/2001 SC140 DSP Core Reference Manual This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright Agere Systems Inc., 2001. All rights reserved.

core i7 alu

Abstract: a836 d859 IR LFN STRT0 SC100 SC110 pic book
Contextual Info: MNSC110CORE/D Rev. 1, 4/2001 SC110 DSP Core Reference Manual MNSC110CORE/D Rev. 1, 4/2001 SC110 DSP Core Reference Manual This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright Agere Systems Inc., 2001. All rights reserved.

l24ca

Abstract: 25LVD
Contextual Info: Preliminary Data Sheet March 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series

data sheet transistor 9014 c V2

Abstract: 9014 general purpose npn transistor wic 6020 cbm 2090 7495 ic divide-by-6 LSC series Microcontroller by MOTOROLA keyboard encoder schematic sab 8216 transistor 2n 7849 data sheet ic 7495
Contextual Info: Advisory July 2001 T8302 Internet Protocol Telephone Advanced RISC Machine ARM Ethernet QoS Using IEEE ® 802.1q Description The Agere Systems, Inc. Voice over Internet Protocol (VoIP) Phone-On-A-Chip solution currently implements a quality of service (QoS) strategy that uses a proprietary voice packet prioritization scheme called

BL Super p5 sanyo denki

Abstract: BL SUPER P5 PLC Communication cables pin diagram Sanyo Denki Sanyo Denki encoder ap13.6 diode DIODE MOTOROLA B34 l31c sanyo denki stepping tunnel diode General Electric ma 1.5 pfd
Contextual Info: Data Sheet October 2001 ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC Introduction Agere Systems Inc. has developed a new ORCA Series 4 based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on

IR LFN

Abstract: SC100 SC140
Contextual Info: MNSC140CORE/D Rev. 2, 4/2001 SC140 DSP Core Reference Manual MNSC140CORE/D Rev. 2, 4/2001 SC140 DSP Core Reference Manual This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright Agere Systems Inc., 2001. All rights reserved.

94vo r29

Abstract: MIL-P-13949F MIL-G-55636 MIL-P-1394 MIL-P-13949 09H-0BH SMD BERG header PCI62FNG pc motherboard schematics
Contextual Info: Information Manual, Rev. 4 June 2002 Evaluation Kit for USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller Introduction Evaluation Kit Contents Thank you for evaluating the Agere Systems USS344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller. This kit contains everything you need

l11D

Abstract: Sanyo Denki encoder transistor BC 667 ORLI10G TRCV0110G TTRN0110G
Contextual Info: Preliminary Data Sheet July 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series

Sanyo Denki encoder

Abstract: ORLI10G TRCV0110G TTRN0110G STM-16 chips 25LVD L30A
Contextual Info: Preliminary Data Sheet March 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series