ADC DIGITAL CALIBRATION TIME INTERLEAVED Search Results

AT84AD001C

Contextual Info: AT84AD001C Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

Digital Oscilloscope Preamplifier

Abstract: LQFP-144 LQFP-144 footprint AT84AD001B AT84AD001TD-EB LQFP144 3968 diode surface AT84AD001 618FS schematics c band satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

Digital Oscilloscope Preamplifier

Abstract: NEC 2561 nec 2561 block diagram AT84AD001B AT84AD001TD-EB LQFP144 schematics ps satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

AT84AD004BVTD

Abstract: Digital Oscilloscope Preamplifier AT84XAD004TD LQFP144 AT84AD004 AT84AD004B ADC digital calibration time interleaved
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

AT84AD004BVTD

Abstract: AT84AD004B Digital Oscilloscope Preamplifier 144L AT84AD004 LQFP144 AT84AD004BVT
Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

radar 77 ghz

Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD001B

Abstract: AT84AD001BVEPW AT84AD001BITD AT84AD001BV
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

satellite tuner sharp

Abstract: AT84AD001B
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD001BVEPW

Abstract: AT84AD001B AT84AD001BV
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD001B

Abstract: AT84AD001BITD
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

Contextual Info: ISL6595 Data Sheet February 27, 2006 Digital Multiphase Controller Features The ISL6595 digital multiphase controller provides core power for today’s high current microprocessors by driving up to six synchronous-rectified buck-converter channels in parallel. Interleaved timing of the channels results in a higher

ISL6595 internal registers

Abstract: kfd2 ISEN138 ISL6595 ISL6595DRZ ISL6595DRZ-T VR10 VR11 powercode
Contextual Info: ISL6595 Data Sheet February 27, 2006 Digital Multiphase Controller Features The ISL6595 digital multiphase controller provides core power for today’s high current microprocessors by driving up to six synchronous-rectified buck-converter channels in parallel. Interleaved timing of the channels results in a higher

ISL6595 internal registers

Abstract: JES22-A114-B 288a ISEN138 ISL6595 ISL6595DRZ-T ISL6595DRZ-TK TB347 VR10 VR11
Contextual Info: ISL6595 Data Sheet May 5, 2008 Digital Multiphase Controller Features The ISL6595 digital multiphase controller provides core power for today’s high current microprocessors by driving up to six synchronous-rectified buck-converter channels in parallel. Interleaved timing of the channels results in a higher

powercode

Contextual Info: ISL6595 Data Sheet December 4, 2008 Digital Multiphase Controller Features The ISL6595 digital multiphase controller provides core power for today’s high current microprocessors by driving up to six synchronous-rectified buck-converter channels in parallel. Interleaved timing of the channels results in a higher

ADC12D1000

Contextual Info: ADC12D1000, ADC12D1600 www.ti.com SNAS480L – MAY 2010 – REVISED OCTOBER 2012 ADC12D1000/ADC12D1600 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC Check for Samples: ADC12D1000, ADC12D1600 FEATURES 1 • 2 • • • • • • • Configurable to either 2.0/3.2 GSPS interleaved

AT84AD004

Abstract: AT84AD004B TP101 TP-101 0818C 0820C ps 4512 diode
Contextual Info: AT84AD004-EB Evaluation Kit User Guide Table of Contents Section 1 Introduction . 1-1 1.1 1.2 Scope .1-1

folding-ADC

Abstract: cherkassky Massana 2114 SRAM differential pair cascode folded cascode folded cascode second stage
Contextual Info: Copyright 2005IEEE. Reprinted from the IEEE Journal of Solid-State Circuits December 2004. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of National Semiconductor's products or services. Internal or personal use of this material

5388b

Abstract: AT84AD004B AT84AD004BVTD AT84AD004-EB AT84AD004 TP101 TP-101 AT84AD004BCTD
Contextual Info: AT84AD004-EB Evaluation Kit . User Guide Table of Contents Section 1 Introduction . 1-1

LQFP-144 recommended layout

Abstract: AT84AD001B AT84AD001BCTD TP101 TP-101
Contextual Info: AT84AD001-EB Evaluation Kit . User Guide Table of Contents Section 1 Introduction . 1-1

transformer ts-170

Abstract: AT84AD001-EB LQFP-144 footprint AT84AD001B AT84AD001BCTD AT84XAD001BTD TP101 TP-101 AT84AD001 10 GSPS ADC FR4
Contextual Info: AT84AD001-EB Evaluation Kit . User Guide Table of Contents Section 1 Introduction . 1-1

AT84AD004B

Abstract: AT84AD004-EB IN 5388A transformer ts-170 AT84AD004 AT84AD004CTD AT84XAD004TD TP101 TP-101 ps 4512 diode
Contextual Info: AT84AD004-EB Evaluation Kit . User Guide Table of Contents Section 1 Introduction . 1-1

AT84AD001B

Abstract: AT84AD001BCTD TP101 TP-101 K Type TP-101 LQFP-144 recommended layout
Contextual Info: AT84AD001-EB Evaluation Kit User Guide Table of Contents Section 1 Introduction . 1-1 1.1 1.2 Scope .1-1

ADC digital calibration time interleaved

Abstract: 56GSa AVD33 10VPPD 56Gs Fujitsu Fujitsu "Evaluation Board" BATBOARD
Contextual Info: 56GSa/s 8-bit Analog-to-Digital Converter VSS VDD AVSADC AVDADC AVD33 AVDNEG AVS AVDRF AVDBB AHIP I ADC AHIN ADC Digital PLL REFS HREF 4:1 AHQP Q ADC AHQN RREF REFCLKP ‚N CLKDIV CAL_OVRRNG SPI_IN XSS I ADC AVIN ADC Digital PLL REFS AVQP 56GSa/s ADC Two-Channel Version Using CHAIS Architecture