MINI-CIRCUITS T4-6T
Abstract: dds phase noise application note
Text: Driving Converters January 2000 Agenda ! DRIVING HIGH SPEED ADC’S ! INTERFACING TO HIGH-SPEED DAC’S ! CLOCK CONSIDERATIONS FOR HIGH SPEED ADC’S AND DAC’S 2 DRIVING HIGH SPEED ADC’S ADC DRIVER REQUIREMENTS AND PERFORMANCE TRADE-OFFS ! Input Driver Circuitry can often be Limiting Factor in Achieving Rated
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AD9226
12-bit
log10
MINI-CIRCUITS T4-6T
dds phase noise application note
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AD9234
Abstract: J306 J406 SO8M1 AD9240-EB panasonic inverter manual Crystal oscillator r315 motorola D213 user guide manual SMHU C517
Text: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FEATURES FUNCTIONAL BLOCK DIAGRAM STANDARD USB 2.0 HSC-ADC-EVALB-SC OR HSC-ADC-EVALB-DC SINGLE OR DUAL HIGH-SPEED ADC EVALUATION BOARD FILTERED ANALOG INPUT REG ADC EQUIPMENT NEEDED Analog signal source and antialiasing filter
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EB05870-0-2/06
AD9234
J306
J406
SO8M1
AD9240-EB
panasonic inverter manual
Crystal oscillator r315
motorola D213 user guide
manual SMHU
C517
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C3538
Abstract: c1826 2-174225-5 ADC highspeed converter AD9225-EB AD922x* datasheet AD9200SSOP-EVAL AD9203-EB MC100EP31 AD9280-EB
Text: PRELIMINARY TECHINICAL DATA High-Speed ADC FIFO Evaluation Kit a Preliminary Technical Data The evaluation kit is easy to setup. Other equipment needed includes an Analog Devices high-speed ADC evaluation board, a power supply, a signal source, and a clock source.
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CY7C68013-128AXC
Abstract: SEMICONDUCTOR J601 u504 AD9234 AD9461 J406 ND R315 CMOS J601 AD9201-EVAL j316
Text: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FEATURES FUNCTIONAL BLOCK DIAGRAM STANDARD USB 2.0 HSC-ADC-EVALB-SC OR HSC-ADC-EVALB-DC SINGLE OR DUAL HIGH-SPEED ADC EVALUATION BOARD FILTERED ANALOG INPUT REG ADC EQUIPMENT NEEDED Analog signal source and antialiasing filter
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EB05870-0-2/06
CY7C68013-128AXC
SEMICONDUCTOR J601
u504
AD9234
AD9461
J406
ND R315
CMOS J601
AD9201-EVAL
j316
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CY7C68013-128AXC
Abstract: SO8M1 J406 national E306 AD9218-105PCB
Text: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FUNCTIONAL BLOCK DIAGRAM FEATURES STANDARD USB 2.0 HSC-ADC-EVALB-SC OR HSC-ADC-EVALB-DC SINGLE OR DUAL HIGH-SPEED ADC EVALUATION BOARD FILTERED ANALOG INPUT REG ADC EQUIPMENT NEEDED Analog signal source and antialiasing filter
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EB05870-0-2/06
CY7C68013-128AXC
SO8M1
J406 national
E306
AD9218-105PCB
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rcf up 2121
Abstract: AD6624AS
Text: a Four-Channel, 80 MSPS Digital Receive Signal Processor RSP Preliminary Technical Data FEATURES 80 MSPS Wide Band Input (14 linear bit plus 3 RSSI) Dual High Speed Data Input Ports Four Independent Digital Receivers in single package Digital Re-sampling for non-Integer Decimation rates
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IS136,
128-Lead
rcf up 2121
AD6624AS
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AD6624AS
Abstract: cic filter AD6600 AD6624 AD9042 IS136 SDFE-2 SDFE-1
Text: Four-Channel, 80 MSPS Digital Receive Signal Processor RSP a PRELIMINARY TECHNICAL DATA FEATURES 80 MSPS Wide Band Inputs (14 linear bit plus 3 RSSI) Dual High Speed Data Input Ports Four Independent Digital Receivers in single package Digital Re-sampling for non-Integer Decimation rates
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AD6624
AD6624AS
cic filter
AD6600
AD6624
AD9042
IS136
SDFE-2
SDFE-1
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SDFE-1
Abstract: No abstract text available
Text: Four-Channel, 80 MSPS Digital Receive Signal Processor RSP a PRELIMINARY TECHNICAL DATA FEATURES 80 MSPS Wide Band Inputs (14 linear bit plus 3 RSSI) Dual High Speed Data Input Ports Four Independent Digital Receivers in single package Digital Re-sampling for non-Integer Decimation rates
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IS136,
AD6624
SDFE-1
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AD6600
Abstract: AD6635 AD6635BBC IS136 cic 2133 rake receiver over slow fading
Text: PRELIMINARY TECHNICAL DATA Four-Channel, 80 MSPS WCDMA Receive Signal Processor RSP a Preliminary Technical Data AD6635 FEATURES APPLICATIONS Four 80 MSPS Wide Band Inputs (14 linear bit plus 3 RSSI) Processes 4 WCDMA channels (UMTS or cdma2000 1x) or 8
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AD6635
cdma2000
IS136
16-bit
20-bits
AD6600
AD6635
AD6635BBC
cic 2133
rake receiver over slow fading
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1agcd
Abstract: No abstract text available
Text: PRELIMINARY TECHNICAL DATA Eight-Channel, 80 MSPS WCDMA Receive Signal Processor RSP a Preliminary Technical Data AD6635 FEATURES APPLICATIONS 80 MSPS Wide Band Inputs (14 linear bit plus 3 RSSI) Processes 4 WCDMA channels (UMTS or cdma2000 1x) or 8 GSM/EDGE, IS136 channels
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AD6635
IS136,
cdma2000
IS136
16-bit
0x000
20-bits
1agcd
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AD9042
Abstract: IS136 AD6600 AD6634 AD6634BBC LA3 DR2
Text: PRELIMINARY TECHNICAL DATA Dual-Channel, 80 MSPS WCDMA Receive Signal Processor RSP a Preliminary Technical Data AD6634 APPLICATIONS 80 MSPS Wide Band Inputs (14 linear bit plus 3 RSSI) Processes 2 WCDMA channels (UMTS or cdma2000 1x) or 4 GSM/EDGE, IS136 channels
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AD6634
cdma2000
IS136
16-bit
0x000
AD9042
AD6600
AD6634
AD6634BBC
LA3 DR2
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