ACT DA HEN NW Search Results

Contextual Info: O K I Semiconductor MSM6322_ PITCH CONTROL LSI FOR THE SPEECH SIGNAL GENERAL DESCRIPTION The MSM6322 converts in realtim e the pitch of the speech signal in a range of one octave u p w ard or dow nw ard. Tw o pitch control m ethods can be selected. O ne is to change the pitch in 17 steps by tw o

CY7C4211-15JI

Abstract: CY7C4201 CY7C4211 CY7C4221 CY7C4231 CY7C4241 CY7C4251 CY7C4421 IDT722X1 nl26
Contextual Info: fax id: 5409 •>* CY7C4421/4201 /4211/4221 CY7C4231/4241/4251 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Functional Description Features • H ig h-speed , low -pow er, first-in , first-o u t F IF O m em o ries • 6 4 x 9 (C Y 7 C 44 21 ) • 256 x 9 (C Y 7 C 4 2 0 1 )

chrysler sci

Abstract: chrysler ccd chrysler ccd bus CD68HC cd68hc68 68HC05 chrysler ic CDP68HC05 CDP68HC05C4 CDP68HC68S1
Contextual Info: CDP68HC68S1 Semiconductor Serial Multiplexed Bus Interface A pril 1994 Features Description • Differential Bus for Minimal EMI T he C D P 68H C 6S S 1 S erial Bus Interface C hip SBIC provides a m eans of interfacing in a S m all A rea N e tw o rk configuration,

Contextual Info: CY7C4421/4201/4211/4221 CY7C4231/4241/4251 WS0 CYPRESS 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs • Low operating power I X 2 = 50 mA • Output Enable (OE pin • 32-pin PLCC/TQFP Features • 64 x 9 (CY7C4421) • 256 x 9 (CY7C4201) • 512 x 9 (CY7C4211)

Contextual Info: «f c y p r e s s PRELIMINARY CY7B4679 10BASE-T/1OBASE-FL Media Converter Features B id irec tio n a l 10 B A S E -T /1 0 B A S E -F L m edia co n ve rsio n M ax im u m lc c o f 120 m A M axim um fib e r-o p tic tra n s m itte r LED c u rren t 110 m A The C Y 7B 4679 10B A S E -F L fibe r-op tic tra n sm itte r offers a fu l­

characteristics of twisted pair cable

Abstract: Twisted Pair twisted pair cable with parameter CY7B4663 CY7B4679 CY7B4679-JC circuit diagram of optical fiber link transmitter id-5011
Contextual Info: f ax id: 5011 i , * " : -:V:V:V:V:V:Tÿ:- : i :^ ^3»* ^ ; i ; i M m i : M M : i : i i ^ iiiiiiyy c ypr ess PRELIMINARY CY7B4679 10BASE-T/1OBASE-FL Media Converter Features B id irectio n al 10B A S E -T /1 0 B A S E -F L m edia co n versio n M axim u m lc c o f 120 m A

B F M 48

Contextual Info: fax id: 5414 CYPRESS PRELIMINARY 256/512/1K/2K/4K/8K x 9 x 2 Dual Sync FIFOs Functional Description Features Dual high sp eed , low pow er, first-in firs t-o u t F IF O m e m o ries Dual 256 x 9 (C Y7C 4801 ) Dual 512 x 9 (C Y 7C 4811) Dual 1 K x 9 (C Y 7 C 48 21 )

Contextual Info: fax id: 1076 Y CY7C1337 32K x 32 Synchronous-Pipelined Cache RAM Feat u res Functional Description Low 660 |iW standby p ow er (f=0, L version) Supports 117-M Hz bus operations with zero wait states Fully registered inputs and o utputs for pipelined o p e r­

ALY SMD

Abstract: 5962-9096501MUC actel a1240 176-CPGA actel 1240a 1240A ST
Contextual Info: ACTEL CORP b7E D • 0 1 = 1 2 4 ^ □ □ □ □ eì3cì 3SD ■ ACT ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features • U p to 2000 G ate A rray G ates 6000 P L D e q u iv alen t g ates • R eplaces up to 53 T T L P ackages

Er 38 transformer

Contextual Info: rZT SGS-THOMSON ST5410 2B1Q U INTERFACE DEVICE A D V A N C E DATA G EN E R AL FEATURES . SINGLE CHIP 2B1Q LINE CODE TR AN S­ CEIVER • SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS ■ MEETS OR EXCEEDS ANSI T 1 .601-1988 U.S. STANDARD ■ MEETS OR EXCEEDS ST/LAA/ELR/822

Contextual Info: MITSUBISHI SOUND PROCESSOR ICs M51564P OPTICAL PICKUP SERVO CONTROL DESCRIPTION The M 51564P is a semiconductor integrated circuit built-in the logic control, servo amplifier and switches required for servo control of CD player pickup. FEATURES • The amplifier, switches and logic control, all requirements

ST5410

Abstract: pin diagrom of 4 bit up down counters stt4 st5410c cl-gd STS410 1554k
Contextual Info: /TT SGS-THOMSON ST5410 6 * [ S Î It iC T M 0 g S 2B1Q U INTERFACE DEVICE A D V A N C E DATA G EN E R AL FEATURES • SINGLE CHIP 2B1Q LINE CODE TR AN S­ CEIVER ■ SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIO NS ■ MEETS OR EXCEEDS ANSI T 1 .601 -1988

5M42

Abstract: 4257A 4257AP
Contextual Info: MITSUBISHI LSIs WP M5M4257AP,J,L-85,-10,-12,-15 NIBBLE MODE 2 6 2 1 4 4 -B IT 2 6 2 1 4 4 -W O R D BY 1-B IT DYNAMIC RAM DESCRIPTIO N This is a fam ily o f 262144 -w o rd by 1-bit dynam ic RAMs, PIN C O N F IG U R A T IO N (TOP V IE W ) fabricated w ith the high performance N-channel silicon gate

RTL8168

Abstract: pci realtek programming 9SC46 RTL8168 EEE Realtek RTL8168 Realtek program rtl8168 programming guide schematic ETHERNET REALTEK Realtek Semiconductor RTL8168 REALTEK
Contextual Info: «M REALTEK R T L 8168 INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS DATASHEET Rev. 1.1 05 November 2004 Track ID: JATR-Í076-21 Realtek Semiconductor Corp. REALTEK No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan

Contextual Info: fax id: 1080 CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Featu res Funct ional Description T h e C Y 7 C 1 329 is 3.3 V 64 K by 32 synch ron ous-p ip eline d cache SR AM designed to su p p o rt zero w a it state seco nd ary cache with m inim al glue logic.

bd847

Abstract: AM79C830 bdp 286 NP10 "Advanced Micro Devices" rafi date BdP 285 AMD Supernet
Contextual Info: P R E L IM IN A R Y Advanced Micro Devices Am79C830 FORMAC Plus DISTINCTIVE CHARACTERISTICS • ■ Im p lem en ts the FDDI M edia Access Control M A C layer protocol for ISO standard 9314-2 ■ Pointers to claim and beacon fram es ■ Su pp orts transm it linked-list addressing

Contextual Info: V CYPRESS CY7C4261 CY7C4271 PRELIMINARY 16K/32Kx 9 Synchronous FIFOs Features Functional Description • 16K x 9 CY7C4261 • 32K x 9 (CY7C4271) • High-speed 100-MHz operation (10 ns read/write cycle time) • Pin-compatible density upgrade to CY7C42X1 family

IN4025

Abstract: 7C43
Contextual Info: CY7C439 _PRELIM INARY ^ SEMICONDUCTOR Bidirectional 2K x 9 FIFO Features Functional Description • 2048 x 9 FIFO buffer memory T h e CY7C439 is a 2048 x 9 F IF O m em ory capable o f bidirectional operation. As the term first-in first-out F IF O implies, data

ADE-602-156

Abstract: RF 433 RR3 hitachi l200 2h2a0 ATI 216 bga ero IEC 384 14/2 fire alarm using IC 555 doc ic laf 0001 laf 0001 power MAS 10 RCD
Contextual Info: SuperH SH 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Hardware Manual HITACHI ÄDE-602-124A Rev. 2.0 03/02/99 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

lexic

Abstract: LEB128 B128 7 segmen Unix International app abstract
Contextual Info: Tool Interface Standards TIS DWARF Debugging Information Format Specification Version 2.0 TIS Committee May 1995 The TIS Committee grants you a non-exclusive, worldwide, royalty-free license to use the information disclosed in the Specifications to make your software TIS-compliant; no other license, express or implied, is granted or intended hereby.

IC 4093 pin configuration

Abstract: IC 4093 pin block diagram IC 4093 14 pin configuration IC 4093 time counter EM 4093 PAEAA act da hen nw IC 2 5/LKB-0722KA 72V841 72V851
Contextual Info: 3.3 VOLT DUAL CMOS SyncFlFO DUAL 256 X 9, DUAL 512 X 9, DUAL 1,024 X 9, DUAL 2,048 X 9, DUAL 4,096 X 9 and DUAL 8,192 X 9 FEATURES: • • • • • • • • • • • • • • • IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 IDT72V851 Each of the two FI FOs designated FI FO A and FI FO B contained in the

M5M41001BP

Abstract: 5M41001
Contextual Info: MITSUBISHI LSIs M5M41001BP, J, L-7, -8,-10 N IB B LE MODE 1 0 4 8 5 7 6 - B IT 1 0 4 8 5 7 6 - W 0 R D BY 1-BIT DYNAMIC RAM D E SC R IP T IO N This is a fam ily o f 1 0 4857 6-w o rd by 1-bit dynam ic RAMs, PIN C O N F IG U R A T IO N (TOP VIEW ) fabricated w ith the high performance C M O S process, and

sk 8085

Abstract: interfacing of memory devices with 8085 8085 opcode STGNF TDA 1111 sp tt 2194 z8 64k series Z8 ROMless Z86L81 Z86L85
Contextual Info: Z 8 L Z 8 6 L 8 1 /8 5 Low-Power ROMless Microcomputer Preliminary Z ilo g 'H lr Prod" c* Specification A p r il 1985 • Complete microcomputer, 24 I/O lines, and up to 64K bytes of addressable external space each for program and data memory. ■ Full-duplex UART and two program m able 8 -bit

1NV04

Abstract: 1nv04 s transistor bl p87 sfe 6.5MHz Filter p8E transistor block diagram of mri machine sfe 6.5MHz M30620ECFP purol 180 mitsubishi alpha xl application
Contextual Info: M itsubishi m icrocom puters M Description 1 6 C /6 2 S IN G L E -C H IP 1 6 -B IT C M O S G ro u p m ic r o c o m p u t e r Description The M 16C /62 group of single-chip m icrocom puters are built using the high-perform ance silicon gate C M OS pro cess using a M 16C /60 S eries C PU core and are p ackaged in a 100-pin pla stic m olded QFP. T h e se