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    ACP UPS Search Results

    ACP UPS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LPR6235-253L Coilcraft Inc Step-up transformer, SMT, RoHS Visit Coilcraft Inc
    LPR6235-123Q Coilcraft Inc Step-up transformer, SMT, RoHS Visit Coilcraft Inc
    LPR6235-752R Coilcraft Inc Step-up transformer, SMT, RoHS Visit Coilcraft Inc
    LPR6235-253P Coilcraft Inc Step-up transformer, SMT, RoHS Visit Coilcraft Inc
    LPR6235-752S Coilcraft Inc Step-up transformer, SMT, RoHS Visit Coilcraft Inc

    ACP UPS Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP


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    SPEAr1340 DDR3-1066, DDR2-1066 533MHz) 16-/32-bit, PDF

    H.264 encoder cortex a8

    Abstract: arm cortex a9 cortex-a9 CMOS Sensor 1080p H.264 60 android mobile MOTHERBOARD CIRCUIT diagram 667 transistor ecb CHINA TV uoc ARm cortexA9 GPIO android mobile circuit diagram "ARM Cortex A9"
    Text: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP


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    SPEAr1340 DDR3-1066, DDR2-1066 533MHz) 16-/32-bit, H.264 encoder cortex a8 arm cortex a9 cortex-a9 CMOS Sensor 1080p H.264 60 android mobile MOTHERBOARD CIRCUIT diagram 667 transistor ecb CHINA TV uoc ARm cortexA9 GPIO android mobile circuit diagram "ARM Cortex A9" PDF

    arm cortex a9

    Abstract: H.264 encoder cortex a8 "ARM Cortex A9" cmos digital camera module MMC 4.2 "NOR Flash controller" H.264 codec PD46 Dual-core ARM Cortex-A9 CPU cortex-a9
    Text: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − production data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP


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    SPEAr1340 DDR3-1066, DDR2-1066 533MHz) 16-/32-bit, arm cortex a9 H.264 encoder cortex a8 "ARM Cortex A9" cmos digital camera module MMC 4.2 "NOR Flash controller" H.264 codec PD46 Dual-core ARM Cortex-A9 CPU cortex-a9 PDF

    arm cortex a9

    Abstract: RMII PHY H.264 codec rgb led 16X32 encoder h.264 CMOS Sensor 1080p H.264 60 Tablets DIAGRAM SPEAR13 how to flash an android media "ARM Cortex A9"
    Text: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP


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    SPEAr1340 DDR3-1066, DDR2-800) 16-/32-bit, arm cortex a9 RMII PHY H.264 codec rgb led 16X32 encoder h.264 CMOS Sensor 1080p H.264 60 Tablets DIAGRAM SPEAR13 how to flash an android media "ARM Cortex A9" PDF

    PEB3465

    Abstract: PEB 4165 T PEB31665 dcnc PEB 4166 T P-MQFP-80-1 smd marking KH PEB31664 PEB31666 PEB4164
    Text: Dat a Sh eet , DS1 , Ju ly 20 00 QAP Q u a d A n a lo g P O TS PEB 3465 Version 1.2 W ir e d C o m mu n i ca t io n s N e v e r s t o p t h i n k i n g . Edition 2000-07-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany


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    D-81541 PEB3465 PEB 4165 T PEB31665 dcnc PEB 4166 T P-MQFP-80-1 smd marking KH PEB31664 PEB31666 PEB4164 PDF

    PEB4266

    Abstract: DuSLIC tc 7680 application notes PEB4266 SEL24 infineon IOM2 "application note" PCMC1 PEB4265 peb3264
    Text: A pplica tion N ote , D S 1, A ug. 2000 DuSLIC PEB 3264/-2 PEB 3265 PEB 4264/-2 PEB 4265/-2 PEB 4266 Version 1.1 / 1.2 / 1.3 External Components Wired Communications N e v e r s t o p t h i n k i n g . Revision History: 2000-08-30 DS 1 Previous Version: Page


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    PDF

    TPC 8A10

    Abstract: No abstract text available
    Text: a FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 6.02 dB Steps over a 48.16 dB Range Low Distortion at 60 dBmV Output –63 dBc SFDR at 21 MHz –57 dBc SFDR at 42 MHz Output Noise Level –47 dBmV in 160 kHz Maintains 75 ⍀ Output Impedance


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    AD8327 AD8327 B5008 CX6002 B5009 C02653â 20-Lead RU-20) TPC 8A10 PDF

    TOKO617DB

    Abstract: AD8327 AD8327ARU AD8327ARU-REEL AD8327-EVAL RU-20 TP10
    Text: a FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 6.02 dB Steps over a 48.16 dB Range Low Distortion at 60 dBmV Output –63 dBc SFDR at 21 MHz –57 dBc SFDR at 42 MHz Output Noise Level –47 dBmV in 160 kHz Maintains 75 ⍀ Output Impedance


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    AD8327 AD8327 B5008 CX6002 B5009 C02653­ 20-Lead RU-20) TOKO617DB AD8327ARU AD8327ARU-REEL AD8327-EVAL RU-20 TP10 PDF

    acp ca14

    Abstract: AD29 AD30 TXC-05551 CA6 SOT l9111 cma1 s c12 virtual-circuit
    Text: SARA II Segmentation and Reassembly Device TXC-05551 DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION • Full duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction • Integrated SONET/SDH 155.52 Mbit/s framer. • Optional 8-bit UTOPIA interface


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    TXC-05551 TXC-05551-MB acp ca14 AD29 AD30 TXC-05551 CA6 SOT l9111 cma1 s c12 virtual-circuit PDF

    toko a55

    Abstract: No abstract text available
    Text: a FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0.75 dB Steps over a 53.5 dB Range Low Distortion at 65 dBmV Output –62 dBc SFDR at 21 MHz –58 dBc SFDR at 65 MHz 1 dB Compression of 25 dBm at 10 MHz Output Noise Level


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    AD8326 AD8326ARP C01856â toko a55 PDF

    X32B

    Abstract: 00BF sot 23
    Text: BACK SARA-2 ATM Cell Processing IC Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Functionality enabled by application-specific microcode e.g., SARA-Lite Microcode • Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction


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    TXC-05551 sche6-9453 TXC-05551-MB X32B 00BF sot 23 PDF

    tp-104-01-00

    Abstract: TOKO transformer TP-104-01-04 TP-104-01 toko pulse transformer 67 AD8326 AD8326ARE AD8326ARE-EVAL 0R155 AD8326ARP
    Text: a FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0.75 dB Steps over a 53.5 dB Range Low Distortion at 65 dBmV Output –62 dBc SFDR at 21 MHz –58 dBc SFDR at 65 MHz 1 dB Compression of 25 dBm at 10 MHz Output Noise Level


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    AD8326 AD8326ARP AD8326ARE 28-Lead RE-28) C01856 tp-104-01-00 TOKO transformer TP-104-01-04 TP-104-01 toko pulse transformer 67 AD8326 AD8326ARE-EVAL 0R155 AD8326ARP PDF

    toko pulse transformer 67

    Abstract: TOKO 100KHz transformer
    Text: a High Output Power Programmable CATV Line Driver AD8326 FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0.75 dB Steps over a 53.5 dB Range Low Distortion at 65 dBmV Output –62 dBc SFDR at 21 MHz –58 dBc SFDR at 65 MHz


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    AD8326 28-Lead RE-28) C01856 toko pulse transformer 67 TOKO 100KHz transformer PDF

    AD29

    Abstract: AD30 TXC-05551 RH -005c RELAY
    Text: SARA-2 ATM Cell Processing IC Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Functionality enabled by application-specific microcode e.g., SARA-Lite Microcode • Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction


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    TXC-05551 AD29 AD30 TXC-05551 RH -005c RELAY PDF

    RQ-20

    Abstract: 622111
    Text: 5 V Upstream Cable Line Driver AD8328 FUNCTIONAL BLOCK DIAGRAM FEATURES BYP AD8328 DIFF OR SINGLE INPUT AMP VIN+ VIN– VOUT+ ATTENUATION CORE VERNIER POWER AMP ZOUT DIFF = 300Ω 8 ZIN SINGLE = 800Ω ZIN (DIFF) = 1.6kΩ VOUT– DECODE 8 DATA LATCH POWER-DOWN


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    AD8328 20-Lead RQ-20 622111 PDF

    Untitled

    Abstract: No abstract text available
    Text: 3.3 V Upstream Cable Line Driver AD8324 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM BYP VIN+ VIN– VOUT+ DIFF OR SINGLE INPUT AMP ATTENUATION CORE VERNIER OUTPUT STAGE VOUT– ZIN SINGLE = 550Ω ZIN (DIFF) = 1100Ω 8 ZOUT DIFF = 75Ω DECODE 8 AD8324


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    AD8324 20-Lead 8-19-2008-A MO-137-AD 04-09-2012-B CP-20-1 PDF

    AD8328

    Abstract: No abstract text available
    Text: 5 V Upstream Cable Line Driver AD8328 FUNCTIONAL BLOCK DIAGRAM FEATURES BYP AD8328 DIFF OR SINGLE INPUT AMP VIN+ VIN– VOUT+ ATTENUATION CORE VERNIER POWER AMP ZOUT DIFF = 300Ω 8 ZIN SINGLE = 800Ω ZIN (DIFF) = 1.6kΩ VOUT– DECODE 8 DATA LATCH POWER-DOWN


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    AD8328 20-Lead AD8328 PDF

    458PT-1556

    Abstract: TGS 832 toko balun AD8324 AD8324ACP AD8324JRQ
    Text: 3.3 V Upstream Cable Line Driver AD8324 FEATURES FUNCTIONAL BLOCK DIAGRAM BYP VIN+ VOUT+ DIFF OR SINGLE INPUT AMP VIN– 8 8 AD8324 POWERDOWN LOGIC RAMP DATA LATCH 8 GND GENERAL DESCRIPTION –50 DATEN DATA CLK 04339-0-001 SHIFT REGISTER –40 Distortion performance of –54 dBc is achieved with an output


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    AD8324 AD8324ACPZ-REEL71 AD8324JRQ-EVAL AD8324ACP-EVAL 20-Lead 458PT-1556 TGS 832 toko balun AD8324 AD8324ACP AD8324JRQ PDF

    Untitled

    Abstract: No abstract text available
    Text: F -2 1 2 INDEX BY BRAND NAME AcceleRate FCC3 0.83mm High Speed Cost-effective Coax Cable Assembly.279 FCS8 0.83mm High Speed Cost-effective Coax Cafcle Socket.279 A c c liM a te " ACP-12 A ccM a te " IP68 Sealed 12mm Cable Assembly_334


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    ACP-12 ACR-12 ACP-16 ACR-16 ACP-22 ACR-22 ate-IP68 PDF

    22-bit

    Abstract: No abstract text available
    Text: S A R A II Segmentation and Reassembly Device TXC-05551 DATA SH EE T PRODUCT PREVIEW FEATURES DESCRIPTION • Full duplex segmentation and reassembly ot multiple VCs up to 155 Mbit/s in each direction • Integrated SONET/SDH 155.52 Mbit/s framer. • Optional 8-bit UTOPIA interface


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    TXC-05551 22-bit PDF

    Untitled

    Abstract: No abstract text available
    Text: SARA -2 X-i t c h DATA SHEET PRODUCT PREVIEW DESCRIPTION Functionality enabled by application-specific microcode e.g., SARA-Lite Microcode Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction Integrated SONET/SDH 155 Mbit/s framer


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    TXC-05551 TXC-05551-MB PDF

    Untitled

    Abstract: No abstract text available
    Text: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction Integrated SONET/SDH 155 Mbit/s framer Optional 8-bit UTOPIA interface


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    TXC-05551 SALI-25C TXC-05551-MB PDF

    Untitled

    Abstract: No abstract text available
    Text: SARA -2 T * A N S W I T C ATM Cell Processing 1C Device TXC-05551 H X- DATA SHEET PRODUCT PREVIEW DESCRIPTION or in their formative • Router information on products • Adapter cards Misc. t Serial EEPROM Interface 4 15 \ 13 PCI Bus „ 49r


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    TXC-05551 32-bit) TXC-05551 TXC-05551-MB PDF

    STM CL-80

    Abstract: acp ca14 AD10 AD14 TXC-05551
    Text: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION Test Access Port SARA-2 is a single-chip solution using feature/ application-specific microcode that performs complete segmentation and reassembly SAR for implementing


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    TXC-05551 SALI-25C TXC-05551 STM CL-80 acp ca14 AD10 AD14 PDF