AAL3 Search Results

wd 969 ir

Abstract: WD 969
Contextual Info: ,'7 $%5 6$5 'HYLFH UUDWD Notes Er rata List Item Chip No. 22  Rev. Symtom Description AAL3/4 receive buffers are Z,BZ,Y, AAL3/4 cells are received incorhandled incorrectly by the ABR BY,CY, rectly. SAR. This condition occurs FY when an AAL3/4 cell that is not

wd 969 ir

Abstract: WD 969
Contextual Info: ,'7 0LFUR $%5 6$5 55$7$ 1RWHV 5(9  (U UDWD /LVW ,WHP &KLS 1R 22  5HY 6\PWRP 'HVFULSWLRQ AAL3/4 receive buffers are Z,BZ,Y, AAL3/4 cells are received incorhandled incorrectly by the Micro BY,CY, rectly. ABR SAR. This condition occurs FY when an AAL3/4 cell that is not

BIT 3195 G

Abstract: marking aal
Contextual Info: T em ic 29C70 MATRA MHS ATM Adaptation Layer Controller for AAL 3/4 and AAL5 Description The 29C70 ATM Adaptation Layer Controller for AAL3/4 and 5 implements CCITT recommentation 1.363. The AAL3/4 and AAL5 are used for data transmission over an ATM Network. The 29C70 is

Contextual Info: Tem ic 29C70 MATRA MHS ATM Adaptation Layer Controller for AAL 3/4 and AAL5 Description T he 29C70 ATM A daptation Layer Controller for AAL3/4 and 5 implements CCITT recom m entation 1.363. The AAL3/4 and AAL5 are used for data transmission over an ATM Network. The 29C70 is

ABSTRACT FOR "Local Interconnect Network"

Abstract: ATM25 BC6911 CRC-10 CRC-32 intel sram ATM management SYSTEM abstract network processor instruction set processor intel intel network controller
Contextual Info: Service-Specific Network Processor Product Bulletin APPLICATIONS • ■ ■ ■ Service-Specific Network Processor DSL or Cable Modem DSL Bridge/Router DSL Access Multiplexer Residential Gateway FEATURES Service-Specific Network Processor Stacks ■ Provisions PPP and ATM over DSL digital subscriber

Contextual Info: 1 N ICStAR O verview The IDT77201 NICStAR PCI ATM Controller is a member of IDT's family of products for Asynchronous Transfer Mode ATM networks. The NICStAR performs both the ATM Adaptation Layer (AAL) Segmentation and Reassem­ bly (SAR) function and the ATM layer protocol functions.

STM CL-80

Abstract: acp ca14 AD10 AD14 TXC-05551
Contextual Info: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION Test Access Port SARA-2 is a single-chip solution using feature/ application-specific microcode that performs complete segmentation and reassembly SAR for implementing

R36W

Abstract: lnk303 samsung ltn LD3130 CRC10 MXT3010 R44-R47 M 8012 R54-R55 t9354
Contextual Info: MXT3010 Reference Manual Version 4.1 Order Number: 100108-05 October 1999 Copyright c 1999 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the

77V011

Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Contextual Info: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.

IDT77222

Abstract: SRA-4 5349
Contextual Info: 155 Mbps ATM SAR CONTROLLER WITH ABR SUPPORT FOR PCI-BASED NETWORKING APPLICATIONS PRELIMINARY INFORMATION IDT77222 Integrated Device Technology, Inc. KEY FEATURES • Full-duplex Segmentation and Reassembly SAR at 155 Mbps "wire-speed" (310 Mbps aggregate speed).

ARM7 samsung

Abstract: S5N8947X 8309 o1m 147 ADSL Modem circuit diagram ADSL MODEM PROGRAMMING Samsung S ARM TAG 70M CRC-10 S5N8947
Contextual Info: S5N8947X MCU for ADSL/Cable Modem Revision 0.1 May. 23, 2000 SAMSUNG ELECTRONICS PROPRIETARY Copyright 1999-2000 Samsung Electronics, Inc. All Rights Reserved S5N8947 (ADSL/Cable Modem MCU) ELECTRONICS CONTENTS 1. GENERAL DESCRIPTION .4

CRC-10

Abstract: PD98401AGD-MML
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98401A ATM SAR CHIP DESCRIPTION The µPD98401A NEASCOT-S15TM is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,

Contextual Info: BROOKTREE CORP b3E I m imss^s 00071Ö4 007 H B R K Interface Specification IS -910.02 PRELIMINARY B id irectio n a l C ell FIF O P a r t # U G A -9 1 0 A p ril, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 6 1 9 -4 5 2 -7 5 8 0

Contextual Info: _ ALI-25C and ALI-25T ATM Line Interface Devices for 25 Mbit/s Operation TXC-07025 Chip Set UJW33 Y ” DATA SHEET DESCRIPTION FEATURES Implements ATM-25 Mbit/s TC and PMD layer functions Supports up to 100 meters of Shielded Twisted Pair STP or Unshielded Twisted Pair types 3,

K 176 LE, K 561 LN

Abstract: AI561
Contextual Info: TNET A1 561 ATM S E G M E N T A T I O N A N D R E A S S E M B L Y D E V I C E WI TH PCI H O S T I N T E R F A C E S D N S 028B-O C TO BER 1994 - REVISED JANUARY 1996 • Per i phe r a l C o m p o n e n t I n t e r c o n n e c t PCI De v i c e T h a t P r o v i d e s A s y n c h r o n o u s

22-bit

Contextual Info: S A R A II Segmentation and Reassembly Device TXC-05551 DATA SH EE T PRODUCT PREVIEW FEATURES DESCRIPTION • Full duplex segmentation and reassembly ot multiple VCs up to 155 Mbit/s in each direction • Integrated SONET/SDH 155.52 Mbit/s framer. • Optional 8-bit UTOPIA interface

Contextual Info: Edition 2.0 1. MB86687A OVERVIEW The ALC simultaneously supports autonomous segmentation and reassembly of user data packets on up to 1024 virtual circuits VCs . User data packets are transferred to and from shared data structure memory using a high speed intelligent DMA

atm header error checking

Abstract: atm header-error-check multiple bit computer networking lan diagram i321
Contextual Info: Introduction to SONET ATM SDNU009A 1–3 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version

mbus

Abstract: SK 8022 ace dsc hen nu SM 8002 C
Contextual Info: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.

1E7d

Abstract: ATM transaction- ABSTRACT atm header error checking msap SN 104 SCR image CRC-10 CRC-32 IDT77211 CRC-32 for FDDI "Border Gateway Protocol"
Contextual Info: IDT77211 NICStAR User Manual Version 1.0 Released Edition February 26, 1997 Find IDT on the World Wide Web at: www.idt.com or Call us at 1-800-345-7015 IDT is located at: 2975 Stender Way Santa Clara, California, USA 95054-3090 0.0 Introduction to the User’s Manual Document

pcr 4063

Abstract: SN 104 SCR image 31136 modem 56k sram OP 8368 0x2f68 IDT77252 ATM machine working circuit diagram bottle filling circuit diagram pti 8504
Contextual Info: IDT77252 ABR SAR User Manual Version 2.3 September 8, 1998 Find IDT on the World Wide Web at: www.idt.com or call us at 1-800-345-7015 IDT is located at: 2975 Stender Way Santa Clara, California, USA 95054-3090 1998 Integrated Device Technology, Inc. Printed U.S.A.

CI EEPROM 2816

Abstract: 31136 modem 56k sram pcr 4063 12697 scd 9104 SN 104 SCR image top 2556 en CRC10 CRC-10
Contextual Info: IDT77222 Micro SAR User Manual Version 1.0 September 8, 1998 Find IDT on the World Wide Web at: www.idt.com or call us at 1-800-345-7015 IDT is located at: 2975 Stender Way Santa Clara, California, USA 95054-3090 1998 Integrated Device Technology, Inc.

interfacing ADC with 8086 microprocessor

Abstract: teaklite 3 instruction opcode MC86000 0.18-um CMOS Flash technology 8086-bus mc8600 I8086 teaklite DRAM 4416 LQPF 208 Package
Contextual Info: S5N8947 DATA SHEET GENERAL DESCRIPTION Samsung's S5N8947 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution. The S5N8947 is designed as 2-channel 10/100Mbps Ethernet controller for use in managed communication hubs and routers. The S5N8947 also provides ATM Layer SAR Segmentation and Reassembly

S4811PBIC

Abstract: Kentrox AMCC s1212 hdlc S1212 Quick Eagle Networks DSLAM structure
Contextual Info: FINAL TIGRIS OC-48 Multi Protocol Termination for 2047 Channels Product FINAL BriefProduct Brief Number S4811PBIC PSIC, Rev. 2008 PartPart Number S4811PBIC PSIC, Rev. 2.5 2.5 JanJan 2008 TIGRIS is a high density data-termination device supporting 2047 channels operating at an aggregate rate of 2.488Gbps. The