AA26 STG Search Results

Contextual Info: 4L* R o c k w e ll Semiconductor Systems RL56CSM/3 Downloadable Digital Central Site Modem Device Introduction Features The RL56CSM/3 is a low-power, digital central site modem system providing three communication channels in a single package. A flexible architecture provides PSTN

Conexant System G24

Abstract: MB-C04 G729 codec ae09 340-PIN HB 8406 k56plus rl56 HB-C06 HBD15
Contextual Info: RL56CSMV/3 and RL56CSM/3 AnyPort Multi-Service Access Processor The RL56CSMV/3 and RL56CSM/3 are members of the Conexant  AnyPort™ family of multi-service access processors, and provide a complete solution to the transport of multiple media types between circuit-switched remote access and a variety of back-end

XC95288

Contextual Info: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

AC1284

Contextual Info: KXILINX XC95288 In-System Programmable CPLD April, 1997 Version 1.0 Preliminary Product Specification Features Description • 15 ns pin-to-pin logic delays on all pins • • • • fcNT t ° MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

Contextual Info: flX IU N X XC95286 In-System Programmable CPLD November 12, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

XC95288

Contextual Info: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

Contextual Info: HXILINX* XC95216 In-System Programmable CPLD April, 1997 Version 1.0 Product Specification Features Power Management • • ns pin-to-pin logic delays on all pins fcNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95216

Contextual Info: EXILINX XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fQNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

Contextual Info: flX IU N X XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

Contextual Info: flXIUNX XC95216 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcN T to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

Contextual Info: flXIUNX XC95288XL High Performance CPLD September 28,1998 Version 1.0 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend­ ing on the system frequency, design application and output

rena3

Abstract: aj7 capacitor Nippon capacitors LCLD25
Contextual Info: MPC8260EC/D Motorola Order Number 11/98 REVO PowerPC Advance Information MPC8260 Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the PowerQUICC H MPC8260

schottky DIODE MOTOROLA B14

Abstract: rena3 schottky DIODE MOTOROLA B12 aa26 stg LCL-05 ti la29 MPC8260 MUR420 T4 w4 DIODE 2sp40
Contextual Info: M j MOTOROLA Motorola Order Number 1/2000 Semiconductor Products Sector REV 0.1 Advance Information MPC8260 Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the PowerQUICC H MPC8260

WPC8763L

Abstract: ATI M64-M QUANTA GD1 C3157 PCI8402 SAMSUNG GDDR3 quanta Neo c480 l3007 cps psi 100u 1p0
Contextual Info: 1 2 3 4 5 1 CPU MEROM GD1 Block Diagram 478 PIN micro FC-PGA P3,4 14.318MHz A A FSB 667 MHz(166X4) FSB 800 MHz(200X4) CLOCK GEN SVideo Out S-Video 32MVRAM 32bits P34 P10 S-Video LCD LVDS P7 CRT R/G/B 32bits P10 ICS9LPR363 P2 P11 LVDS 1299 Ball (micro FCBGA)

alviso-GM

Abstract: ICS954206 pc123 T7 65R77 AOS4916 3RN10 NS681687 LM358 quanta quanta computer
Contextual Info: 1 2 3 4 5 6 7 8 5VPCU BOM MARK Centrino 3V_ALWAYS 5V / 3.3V 15V CLOCK GEN ICS ICS954206 +5V +3V_S5 Kyoto II EW5 PENTIUM-P/CELEROM-M DORTHAN INTEL Mobile_479 CPU Page 3,4 Page 2 A A +3V +3VSUS Page 26 HOST BUS 400/533MHz +5VSUS +1.8VSUS 1.8V / 0.9V CLK_SDRAM0~5,

ni usb 6212

Abstract: SS-00259-1 C2060 C2055 C2068 quanta C2096 R2067 915GM SW1010CPT
Contextual Info: 1 2 3 4 5 478 PIN micro FC-PGA 14, 15, 15w , 17w inch XGA, SXGA+ A LVDS LCD P7 P3,4 400/533 MHz A LVDS Alviso DVI M24/M26 UNBUFFERED DDRII SODIMM DDRII 400/533 P10 915GM/PM R/G/B CRT P9 R/G/B UNBUFFERED DDRII SODIMM DDRII 400/533 1257 PIN (micro FCBGA) PCIE 16Lanes

atmel 0928

Abstract: QUANTA GD1 C3258 max8776 ati c155 100u 1p0 C3257 intel G41 MOTHERBOARD crb l3007 PCI8402 C3261
Contextual Info: 1 2 3 4 5 1 CPU MEROM GD1 Block Diagram 478 PIN micro FC-PGA P3,4 14.318MHz A A FSB 667 MHz(166X4) FSB 800 MHz(200X4) CLOCK GEN SVideo Out S-Video 32MVRAM 32bits P34 P10 S-Video ATI M64 LVDS LCD R/G/B CRT P7 LVDS 29mm x 29mm 32MVRAM 32bits P10 UNBUFFERED

diode marking code e26

Abstract: PIN DIAGRAM of IC AD 524 ultrasparc
Contextual Info: S un M ic r o e l e c t r o n ic s July 1997 U2P DATA SHEET UPA to PCI Interface D e s c r ip t io n The U2P * chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus including UltraSPARC Processors and Memory and a PCI based I/O Subsystem. Its major functions are

transistor P239

Abstract: R33PI transistor 4287 AB P239 9 318 TI P272 w29 transistor P069 P04368 p055 IQB96
Contextual Info: The FPID Family Data Sheet Features Description Device I-Cube's family of FPID devices is available in a variety of I /O densities, ranging from 96 to 320 usable ports. The part number reflects the number of usable I/O s in the device. This family, from the

am3 938 pinout

Abstract: MA 573 U18 524 BN 672 M3
Contextual Info: APEX 20K Programmable Logic Device Family March 2000, ver. 2.06 Data Sheet Features. • Preliminary Information ■ Industry’s first programmable logic device PLD incorporating system-on-a-programmable-chip integration – MultiCoreTM architecture integrating look-up table (LUT) logic,

SW1010CPT

Abstract: PC614 SN0307009B ICS954227 sony lanc Socket AM2 2pc606 PC613 LANc to USB quanta
Contextual Info: 1 2 3 4 5 1 RD1 Block Diagram Dothan 478 PIN micro FC-PGA P3,4 A A 400/533 MHz 14w inch XGA, SXGA+ LCD Alviso P7 AVOUT UNBUFFERED DDRII SODIMM DDRII 400/533 915GM UNBUFFERED DDRII SODIMM DDRII 400/533 CRT P10 P9 P9 1257 PIN (micro FCBGA) P5,6,7,8 P10 DMI

K C2026 Y

Abstract: VT6212 sony C2105 c2078 c2166 C2068 c2096 Marvell 88E8053 C2060 C2076
Contextual Info: 1 2 3 4 5 478 PIN micro FC-PGA 14, 15, 15w , 17w inch XGA, SXGA+ A LVDS LCD P7 P3,4 400/533 MHz A LVDS Alviso DVI M24/M26 UNBUFFERED DDRII SODIMM DDRII 400/533 P10 915GM/PM R/G/B CRT P9 R/G/B UNBUFFERED DDRII SODIMM DDRII 400/533 1257 PIN (micro FCBGA) PCIE 16Lanes

Contextual Info: SME1430LGA-360 SME1430LGA-440 SME1430LGA-480 microsystems May 1999 UltraSPARC -»/CPU DATA SHEET H ighly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces D e s c r ip t io n The SME1430LGA CPU UltraSPARC-Ill microprocessor is a highly-integrated, 64-bit, SPARC V9 superscalar

11AK12

Abstract: 4062XLA Trans Metrics P100 4044XL AD 690 xilinx HQ240 diode ak14
Contextual Info: £ X IU N X XC4000XLA/XV Field Programmable Gate Arrays February 1, 1999 Version 1.0 Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC 4000XLA devices are improved versions of X C 4000X L devices. The XC4000X V devices have the