A18A Search Results

Contextual Info: TMS29F040 524288 BY 8-BIT FLASH MEMORY SMJS820B - APRIL 1996- REVISED NOVEMBER 1987 • • • • • • • • • • Single Power Supply 5 V± 10% - 3.3 V ± 0.3 V - See ’29LF040/’29VF040 Data Sheet Literature Number SMJS825 - 2.7 V to 3.6 V - See ’29LF040/’29VF040

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD48288209, 48288218, 48288236 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209 is a 33,554,432-word by 9 bit, the μPD48288218 is a 16,777,216 word by 18 bit and the μPD48288236 is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology

Z80180

Abstract: Zilog z180 Z8018233FSC Z80180 technical manual Z80182 ESCC technical manual z182 Z180 Z180 mpu Zilog 85230 z180 controller
Contextual Info: Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER ZIP FEATURES • Z8S180 MPU - Code Compatible with Zilog Z80 /Z180™ CPU - Extended Instructions

GL032A

Abstract: S71GL032A S71GL032
Contextual Info: S71GL032A Based MCPs Stacked Multi-Chip Product MCP Flash Memory and RAM 32 Megabit (2 M x 16-bit) CMOS 3.0 Volt-only Page Mode Flash Memory and 16/8/4 Megabit (1M/512K/256K x 16-bit) Pseudo Static RAM Data Sheet ADVANCE INFORMATION Notice to Readers: The Advance Information status indicates that this

PDM31096

Abstract: PDM31096LL
Contextual Info: PDM31096LL PRELIMINARY 512K x 8-Bit Low Power 3.3 Volt Description Features n High-speed access times Com’l: 70, 85 and 100ns n Low power operation typical - PDM31096LL Active: 65 mW Standby: 10µW The PDM31096LL is a very low power CMOS static RAM organized as 524,288 x 8 bits. Writing to this

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

Contextual Info: A M D tl Am29DL800B 8 Megabit 1 M x 8-Bit/512 K x 16-Bit CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS • Simultaneous Read/Write operations — Host system can program or erase in one bank, then immediately and simultaneously read from

20510D

Contextual Info: P R E L IM IN A R Y AMD3 Am29LV004 4 Megabit 512 K x 8-Blt CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS • Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

am29f040b

Contextual Info: AMD3 Am29F040B 4 Megabit 512 K x 8-Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Distinctive Characteristics • 5.0 V ± 10% for read and write operations ■ — Minimizes system level power requirements ■ Manufactured on 0.32 pm process technology

29LV008

Contextual Info: — P R E L IM IN A R Y — AMD Cl Am29LV008T/Am29LV008B 8 Megabit 1,048,576 x 8-Bit CMOS 3.0 Volt-only, Sectored Flash Memory • ■ ■ Single power supply operation ■ — Extended voltage range: 2.7 to 3.6 volt read and write operations for battery-powered

29f800bb

Abstract: 29F800BT 29F800B 29F800BT-70 29F800BT-90 29F800BB-70 M29F800B 29f800bb55
Contextual Info: AMD£I Am29F800B 8 Megabit 1 M x 8-Bit/512 K x 16-Bit CMOS 5.0 Volt-only, Boot Sector Flash Mem ory DISTINCTIVE CHARACTERISTICS • Single power supply operation — 5.0 Volt-only operation for read, erase, and program operations — Minimizes system level requirements

29f004b

Contextual Info: ADVANCE INFORMATION AM D il Am29F004B 4 Megabit 512 K x 8-Bit CMOS 5.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS • ■ 5.0 Volt single power supply operation ■ Top or bottom boot block configurations available — Minimizes system-level power requirem ents

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: CMOS SyncFIFO IDT723611 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B

Contextual Info: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

HY628400LP

Contextual Info: HY628400-I Series 'H Y U N D A I 512KX 8-bit CMOS SRAM PRELIMINARY DESCRIPTION The HY628400-I is a high-speed, low power and 524,288 x 8-bits CMOS static RAM fabricated using Hyundai’s high performance twin tub CMOS process technology. This high reliability process coupled with innovative circuit

Contextual Info: 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • Passive parity checking on each Port • Parity Generation can be selected for each Port • Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: |dy Integrated Dev ice Technology, Inc. CMOS Triple Bus SyncFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY I D T y iii ll IDT723646 FEATURES: • Memory storage capacity: IDT723626-256 x 36 x 2 IDT723636-512 x 3 6 x 2 IDT723646-10 2 4 x 3 6 x 2

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: AT91SAM ARM-based Embedded MPU SAM9263 Description The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent

PX3-2

Abstract: AT32UC3A0256 128f 385P AT32UC3A0512
Contextual Info: Features • High Performance, Low Power 32-Bit Atmel AVR® Microcontroller • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation