A15IZ Search Results

Contextual Info: HM62W1664H Series HM62W1864H Series P r e lim in a r y 65536-word x 16/18-bit High Speed CMOS Static RAM T h e H M 6 2 W 1 6 6 4 H /H M 6 2 W 1 8 6 4 H is an asyncronous 3.3 V operation high speed static RAM organized as 64 kword x 16/18 bit. It realize h ig h sp eed access tim e 2 5 /3 0 /3 5 /4 5 ns w ith

ATT3000

Abstract: ATT3020
Contextual Info: AT&T Data Sheet July 1992 Microelectronics ATT3000 Series Field-Programmable Gate Arrays FEATURES • High Performance— up to 150 MHz Toggle Rates • User-Programmable Gate Array • I/O functions • Digital logic functions • Interconnections • Flexible array architecture

lh531

Abstract: LH531000B LH531000BN-S LH531000B-S
Contextual Info: L H ^ I n n O R l v / V * v u v - C ^ CMOS 1M 128K x 8 w _ 3 V-D rive M a sk-P ro g ram m a ble ROM FEATURES DESCRIPTION • 131,072 words x 8 bit organization The LH531000B-S is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using

Contextual Info: H M 6 2 W 1 6 6 4 H S e r ie s H M 6 2 W 1 8 6 4 H S e r ie s 65536-w ord x Preliminary 16/18-b it High Speed C M O S Static RAM The H M 6 2 W I6 6 4 H /H M 6 2 W I8 6 4 U is an asynchronous 3.3 V o p e ra tio n high speed static R A M organized as 64 kword x 16/18 bit. It realize

Contextual Info: ADV MI CRO ME MO R Y MÖE D D5S7SSÖ ÜD30b37 5 • AMDM T—46—1 3-25 Am27X040 4 Megabit (524,288 x 8-Bit) CMOS ExpressROM Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS ■ As an OTP EPROM alternative: - Factory optimized programming

Contextual Info: XC3000 Logic Celi “Array Family Product Specification FEATURES The LCA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system

HM62W1664HUP-35

Contextual Info: HM62W1664H / HM62W1864H Series 65,536-word x 16/18-bit High Speed CMOS Static RAM HITACHI The H M 6 2 W 1 6 6 4 H /H M 6 2 W 1 8 6 4 H is an Ordering Information a s y n c h ro n o u s 3.3 V o p e ra tio n h ig h s p e e d sta tic R A M o r g a n i z e d a s 6 4 - k w o r d x 1 6 /1 8 - b i t. It

Contextual Info: CMOS 8M 1M x 8 MROM FEATURES • 1,048,576 words x 8 bit organization • Access time: 120 ns (MAX.) PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW 1 • 32 Zl Vcc A ^ IZ 2 31 Zl a 18 A1 5 C 3 30 □ A12IZ 4 29 □ A 14 A7C 5 28 Zl a 13 Aig IZ • Power consumption:

614l

Abstract: BNXXX
Contextual Info: CMOS SyncBiFlFO WITH BUS-MATCHING AND BYTE SWAPPING 64 X 36 X 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

HM658512LP-10V

Abstract: HM658512LP10
Contextual Info: HM658512 Series 524288-Word x 8-Bit High Speed Pseudo Static RAM Features Ordering Information • Single 5 V ±10% • Highspeed - Access time CE access time: 80/85/100/120 ns - Cycle time Random read/write cycle time: 130/160/190 ns • Low power - 250 mW typ active

Contextual Info: MITSUBISHI LSIs M6MGB/T160S2BVP 16,777,216-BIT 1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) DESCRIPTION FEATURES