A12L
Abstract: TSM67V05
Text: TSM67V05 8 K x 8 CMOS Dual Port RAM Low Voltage 3.3 Volt Introduction The TSM67V05 is a very low power CMOS dual port static RAM organized as 8192 x 8. The TSM67V05 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit
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TSM67V05
TSM67V05
A12L
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Untitled
Abstract: No abstract text available
Text: M67025E 8 K 16 CMOS Dual Port RAM Rad Tolerant Introduction The M67025E is a very low power CMOS dual port static RAM organised as 8192 x 16. The M67025E is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or
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M67025E
M67025E
67025EV
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M67005
Abstract: A12L 9419M
Text: MATRA MHS M 67005 8 K x 8 CMOS Dual Port RAM Introduction The M 67005 is a very low power CMOS dual port static RAM organized as 8192 × 8. The M67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or
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M67005
A12L
9419M
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A12L
Abstract: No abstract text available
Text: M67025E 83 K 16 CMOS Dual Port RAM Rad Tolerant Introduction The M67025E is a very low power CMOS dual port static RAM organised as 8192 x 16. The M67025E is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or
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M67025E
M67025E
67025EV
A12L
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A12L
Abstract: No abstract text available
Text: L 67005 MATRA MHS 8 K x 8 CMOS Dual Port RAM 3.3 Volt Introduction The L 67005 is a very low power CMOS dual port static RAM organized as 8192 × 8. The L 67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or
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67005E
Abstract: M67005 A12L CQFP68 P883
Text: M67005 8 K 8 CMOS Dual Port RAM Introduction The M67005 is a very low power CMOS dual port static RAM organized as 8192 x 8. The M67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or
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M67005
M67005
67005E
67005E
A12L
CQFP68
P883
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100-PIN
Abstract: 84-PIN 9515M
Text: M 67025 MATRA MHS 8 K x 16 CMOS Dual Port RAM Introduction The M 67025 is a very low power CMOS dual port static RAM organised as 8192 × 16. The M 67025 is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or
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52887
Abstract: 67025E A12L M67025E MMK2-67025EV-30 MMK2-67025EV-30-E
Text: Features • Fast access time: 30/45 ns • Wide temperature range: – -55°C to +125°C • Separate upper byte and lower byte control for multiplexed bus compatibility • Expandable data bus to 32 bits or more using master/slave chip select when using
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67025E
Abstract: A12L M67025 M67025E Shared resource arbitration
Text: Features • • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146L
67025E
A12L
M67025
M67025E
Shared resource arbitration
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5962-9161709VZC
Abstract: A12L M67025 M67025E
Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146J
5962-9161709VZC
A12L
M67025
M67025E
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5962-9161709VZC
Abstract: M67025E A12L 67025E M67025
Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146J
5962-9161709VZC
M67025E
A12L
67025E
M67025
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5962-9161709qzc
Abstract: A12L M67025 M67025E 5962-9161709VZC MMK267025EV30E Shared resource arbitration
Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146I
5962-9161709qzc
A12L
M67025
M67025E
5962-9161709VZC
MMK267025EV30E
Shared resource arbitration
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Shared resource arbitration
Abstract: No abstract text available
Text: Features • • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146M
Shared resource arbitration
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67025E
Abstract: A12L M67025 M67025E Shared resource arbitration
Text: Features • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
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4146N
67025E
A12L
M67025
M67025E
Shared resource arbitration
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transistor a4L
Abstract: a7l transistor 55AX A12L CY7C144 CY7C145 CY7C CY7C144-15AI
Text: CY7C144 CY7C145 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 8K x 8 organization CY7C144 ■ 8K x 9 organization (CY7C145)
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CY7C144
CY7C145
CY7C144)
CY7C145)
65-micron
transistor a4L
a7l transistor
55AX
A12L
CY7C145
CY7C
CY7C144-15AI
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Untitled
Abstract: No abstract text available
Text: CY7C007A16 K x 8 Dual-Port Static RAM CY7C006A 16 K × 8 Dual-Port Static RAM 16 K × 8 Dual-Port Static RAM Features • Expandable data bus to 16 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■
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CY7C007A16
CY7C006A
CY7C006A)
35-micron
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Untitled
Abstract: No abstract text available
Text: CY7C007A16 K x 8 Dual-Port Static RAM CY7C006A 16 K × 8 Dual-Port Static RAM 16 K × 8 Dual-Port Static RAM Features • Expandable data bus to 16 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■
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CY7C007A16
CY7C006A
CY7C006A)
35-micron
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CY7C09099V
Abstract: No abstract text available
Text: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09099V CY7C09179V 3.3 V 32K/128K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which enable simultaneous access of the same memory location
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09099V
CY7C09179V
32K/128K
K/128
CY7C09179V)
CY7C09099V)
CY7C09099V
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CY7C09099V
Abstract: No abstract text available
Text: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09089V/99V
CY7C09179V/99V
K/128
100-pin
CY7C09099V
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Untitled
Abstract: No abstract text available
Text: CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16 K / 32 K / 64 K x 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM Features • ■ True dual-ported memory cells that allow simultaneous access of the same memory location
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CY7C09269V/79V/89V
CY7C09369V/89V
100-pin
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CYPRESS CROSS REFERENCE dual port sram
Abstract: CY7C006AV CY7C007AV CY7C016AV CY7C017AV CY7C138AV CY7C139AV CY7C144AV CY7C145AV
Text: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous
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CY7C138AV
CY7C139AV
CY7C144AV
CY7C145AV
CY7C006AV
CY7C016AV
CY7C007AV
CY7C017AV
CY7C144AV
CY7C006AV
CYPRESS CROSS REFERENCE dual port sram
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Untitled
Abstract: No abstract text available
Text: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous
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CY7C138AV
CY7C139AV
CY7C144AV
CY7C145AV
CY7C006AV
CY7C016AV
CY7C007AV
CY7C017AV
CY7C006AV
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CY7C09279V
Abstract: CY7C09389V-9AI
Text: CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16 K / 32 K / 64 K x 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells that allow simultaneous access of the same memory location
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CY7C09269V/79V/89V
CY7C09369V/89V
CY7C09269V/369V)
CY7C09279V)
CY7C09289V/389V)
CY7C09279V
CY7C09389V-9AI
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xr1094
Abstract: FIVE band graphic equalizer 261G6 capacitor 106 16K XR1094CP gph-17 xr-1094
Text: XR-1094 X 'E X A R Advanced Information Five Band Graphic Equalizer Filter and Display Driver PIN ASSIGNMENT GENERAL INFORMATION A1 The XR-1094 is a single chip graphic equalizer and display driver containing switched-capacitor band pass filters, filter multiplexer, data latches and high
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XR-1094
XR-1094
16kHz.
10kHz
16kHz
fr60i
xr1094
FIVE band graphic equalizer
261G6
capacitor 106 16K
XR1094CP
gph-17
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