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    A12L TRANSISTOR Search Results

    A12L TRANSISTOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    2SC6026MFV Toshiba Electronic Devices & Storage Corporation NPN Bipolar Transistor / VCEO=50 V / IC=0.15 A / hFE=120~400 / VCE(sat)=0.25 V / SOT-723 Visit Toshiba Electronic Devices & Storage Corporation
    TTC5886A Toshiba Electronic Devices & Storage Corporation NPN Bipolar Transistor / VCEO=50 V / IC=5 A / hFE=400~1000 / VCE(sat)=0.22 V / tf=120 ns / New PW-Mold Visit Toshiba Electronic Devices & Storage Corporation
    TTA2097 Toshiba Electronic Devices & Storage Corporation PNP Bipolar Transistor / VCEO=-50 V / IC=-5 A / hFE=200~500 / VCE(sat)=-0.27 V / tf=60 ns / New PW-Mold Visit Toshiba Electronic Devices & Storage Corporation
    TTC022 Toshiba Electronic Devices & Storage Corporation NPN Bipolar Transistor / VCEO=12 V / IC=5 A / hFE=250~500 / VCE(sat)=0.14 V / tf=50 ns / PW-Mini Visit Toshiba Electronic Devices & Storage Corporation
    TTC020 Toshiba Electronic Devices & Storage Corporation NPN Bipolar Transistor / VCEO=80 V / IC=4 A / hFE=100~200 / VCE(sat)=0.17 V / tf=70 ns / PW-Mini Visit Toshiba Electronic Devices & Storage Corporation

    A12L TRANSISTOR Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    A12L

    Abstract: TSM67V05
    Text: TSM67V05 8 K x 8 CMOS Dual Port RAM Low Voltage 3.3 Volt Introduction The TSM67V05 is a very low power CMOS dual port static RAM organized as 8192 x 8. The TSM67V05 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit


    Original     		TSM67V05 TSM67V05 A12L PDF

    Untitled

    Abstract: No abstract text available
    Text: M67025E 8 K  16 CMOS Dual Port RAM Rad Tolerant Introduction The M67025E is a very low power CMOS dual port static RAM organised as 8192 x 16. The M67025E is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or


    Original     		M67025E M67025E 67025EV PDF

    M67005

    Abstract: A12L 9419M
    Text: MATRA MHS M 67005 8 K x 8 CMOS Dual Port RAM Introduction The M 67005 is a very low power CMOS dual port static RAM organized as 8192 × 8. The M67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or


    Original     		M67005 A12L 9419M PDF

    A12L

    Abstract: No abstract text available
    Text: M67025E 83 K  16 CMOS Dual Port RAM Rad Tolerant Introduction The M67025E is a very low power CMOS dual port static RAM organised as 8192 x 16. The M67025E is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or


    Original     		M67025E M67025E 67025EV A12L PDF

    A12L

    Abstract: No abstract text available
    Text: L 67005 MATRA MHS 8 K x 8 CMOS Dual Port RAM 3.3 Volt Introduction The L 67005 is a very low power CMOS dual port static RAM organized as 8192 × 8. The L 67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or


    Original     		PDF

    67005E

    Abstract: M67005 A12L CQFP68 P883
    Text: M67005 8 K  8 CMOS Dual Port RAM Introduction The M67005 is a very low power CMOS dual port static RAM organized as 8192 x 8. The M67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or


    Original     		M67005 M67005 67005E 67005E A12L CQFP68 P883 PDF

    100-PIN

    Abstract: 84-PIN 9515M
    Text: M 67025 MATRA MHS 8 K x 16 CMOS Dual Port RAM Introduction The M 67025 is a very low power CMOS dual port static RAM organised as 8192 × 16. The M 67025 is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or


    Original     		PDF

    52887

    Abstract: 67025E A12L M67025E MMK2-67025EV-30 MMK2-67025EV-30-E
    Text: Features • Fast access time: 30/45 ns • Wide temperature range: – -55°C to +125°C • Separate upper byte and lower byte control for multiplexed bus compatibility • Expandable data bus to 32 bits or more using master/slave chip select when using


    Original     		PDF

    67025E

    Abstract: A12L M67025 M67025E Shared resource arbitration
    Text: Features • • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146L 67025E A12L M67025 M67025E Shared resource arbitration PDF

    5962-9161709VZC

    Abstract: A12L M67025 M67025E
    Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146J 5962-9161709VZC A12L M67025 M67025E PDF

    5962-9161709VZC

    Abstract: M67025E A12L 67025E M67025
    Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146J 5962-9161709VZC M67025E A12L 67025E M67025 PDF

    5962-9161709qzc

    Abstract: A12L M67025 M67025E 5962-9161709VZC MMK267025EV30E Shared resource arbitration
    Text: Features • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146I 5962-9161709qzc A12L M67025 M67025E 5962-9161709VZC MMK267025EV30E Shared resource arbitration PDF

    Shared resource arbitration

    Abstract: No abstract text available
    Text: Features • • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146M Shared resource arbitration PDF

    67025E

    Abstract: A12L M67025 M67025E Shared resource arbitration
    Text: Features • • • • • • • • • • • • • • • Fast Access Time: 30/45 ns Wide Temperature Range: -55°C to +125°C Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using


    Original     		4146N 67025E A12L M67025 M67025E Shared resource arbitration PDF

    a7r transistor

    Abstract: transistor a4L A12L transistor A0LA A12L CY7C144 CY7C145
    Text: CY7C144 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 8K x 8 organization CY7C144 ■ 8K x 9 organization (CY7C145) ■ 0.65-micron complementary metal oxide semiconductor


    Original     		CY7C144 CY7C144) CY7C145) 65-micron CY7C144 CY7C145 CY7C144/5 a7r transistor transistor a4L A12L transistor A0LA A12L PDF

    transistor a4L

    Abstract: a7l transistor 55AX A12L CY7C144 CY7C145 CY7C CY7C144-15AI
    Text: CY7C144 CY7C145 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 8K x 8 organization CY7C144 ■ 8K x 9 organization (CY7C145)


    Original     		CY7C144 CY7C145 CY7C144) CY7C145) 65-micron transistor a4L a7l transistor 55AX A12L CY7C145 CY7C CY7C144-15AI PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C007A16 K x 8 Dual-Port Static RAM CY7C006A 16 K × 8 Dual-Port Static RAM 16 K × 8 Dual-Port Static RAM Features • Expandable data bus to 16 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■


    Original     		CY7C007A16 CY7C006A CY7C006A) 35-micron PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C007A16 K x 8 Dual-Port Static RAM CY7C006A 16 K × 8 Dual-Port Static RAM 16 K × 8 Dual-Port Static RAM Features • Expandable data bus to 16 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■


    Original     		CY7C007A16 CY7C006A CY7C006A) 35-micron PDF

    CY7C09099V

    Abstract: No abstract text available
    Text: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09099V CY7C09179V 3.3 V 32K/128K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which enable simultaneous access of the same memory location


    Original     		CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09099V CY7C09179V 32K/128K K/128 CY7C09179V) CY7C09099V) CY7C09099V PDF

    CY7C09099V

    Abstract: No abstract text available
    Text: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.


    Original     		CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V K/128 100-pin CY7C09099V PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16 K / 32 K / 64 K x 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM Features • ■ True dual-ported memory cells that allow simultaneous access of the same memory location


    Original     		CY7C09269V/79V/89V CY7C09369V/89V 100-pin PDF

    CYPRESS CROSS REFERENCE dual port sram

    Abstract: CY7C006AV CY7C007AV CY7C016AV CY7C017AV CY7C138AV CY7C139AV CY7C144AV CY7C145AV
    Text: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous


    Original     		CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV CY7C144AV CY7C006AV CYPRESS CROSS REFERENCE dual port sram PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous


    Original     		CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV CY7C006AV PDF

    CY7C09279V

    Abstract: CY7C09389V-9AI
    Text: CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16 K / 32 K / 64 K x 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells that allow simultaneous access of the same memory location


    Original     		CY7C09269V/79V/89V CY7C09369V/89V CY7C09269V/369V) CY7C09279V) CY7C09289V/389V) CY7C09279V CY7C09389V-9AI PDF