A/HC SRD4 Search Results
A/HC SRD4 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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74AC11000DR |
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Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 |
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74AC11008PWR |
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Quadruple 2-Input Positive-AND Gates 16-TSSOP -40 to 85 |
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74AC11138N |
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3-Line to 8-Line Decoders/Demultiplexers 16-PDIP -40 to 85 |
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74ACT11004PW |
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Hex Inverters 20-TSSOP -40 to 85 |
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74ACT11032NE4 |
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Quadruple 2-Input Positive-OR Gates 16-PDIP -40 to 85 |
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A/HC SRD4 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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O2-A2
Abstract: CLA60000 16-LINE TO 4-LINE PRIORITY ENCODERS DRF4T101 4 bit binary multiplier Gray to BCD converter CLA5000 J K flip-flop CLA64 design octal counter using j-k flipflop
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CLA60000 70MHz. O2-A2 16-LINE TO 4-LINE PRIORITY ENCODERS DRF4T101 4 bit binary multiplier Gray to BCD converter CLA5000 J K flip-flop CLA64 design octal counter using j-k flipflop | |
24 volt dc to 110 volt ac inverter schematic
Abstract: O2-A2 CLA62 MVA500
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CLA60000 70MHz. 24 volt dc to 110 volt ac inverter schematic O2-A2 CLA62 MVA500 | |
Contextual Info: PLESSIEY SEMICONDUCTORS Appendix 7 ; CLA60000 SERIES CHANNELLESS CMOS GATE ARRAYS Supersedes December 1988 Edition This advanced family o f gate arrays uses many innovative techniques to achieve 110K gates pa r ch'p - system clock speeds in excess o f 70MHz are achievable. The combinatbn |
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CLA60000 70MHz | |
CLA60000
Abstract: zarlink cla5000 CLA5000 16-LINE TO 4-LINE PRIORITY ENCODERS 4 bit binary multiplier CLA5000 Series Zarlink gate array RAD32D MVA50
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CLA60000 70MHz. zarlink cla5000 CLA5000 16-LINE TO 4-LINE PRIORITY ENCODERS 4 bit binary multiplier CLA5000 Series Zarlink gate array RAD32D MVA50 | |
full subtractor circuit using decoder
Abstract: full subtractor circuit using nor gates tdb 158 dp VHDL program 4-bit adder 8 bit carry select adder verilog codes full subtractor circuit using nand gate full adder circuit using nor gates full subtractor circuit using nand gates full subtractor circuit nand gates 0-99 counter by using 4 dual jk flip flop
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CLA70000 DS2462 full subtractor circuit using decoder full subtractor circuit using nor gates tdb 158 dp VHDL program 4-bit adder 8 bit carry select adder verilog codes full subtractor circuit using nand gate full adder circuit using nor gates full subtractor circuit using nand gates full subtractor circuit nand gates 0-99 counter by using 4 dual jk flip flop | |
full adder circuit using nor gates
Abstract: full subtractor circuit using nand gate full subtractor circuit using nor gates full subtractor circuit using decoder 8 bit carry select adder verilog codes half adder 74 full subtractor circuit nand gates 8 bit subtractor 3 bit carry select adder verilog codes full subtractor circuit using nand gates
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CLA70000 DS2462 full adder circuit using nor gates full subtractor circuit using nand gate full subtractor circuit using nor gates full subtractor circuit using decoder 8 bit carry select adder verilog codes half adder 74 full subtractor circuit nand gates 8 bit subtractor 3 bit carry select adder verilog codes full subtractor circuit using nand gates | |
8 bit carry select adder verilog codes
Abstract: full subtractor circuit using decoder 3 bit carry select adder verilog codes tdb 158 dp gec plessey semiconductor full subtractor circuit using nor gates full adder circuit using nor gates mc2870 VHDL program 4-bit adder 8 bit subtractor
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CLA70000 8 bit carry select adder verilog codes full subtractor circuit using decoder 3 bit carry select adder verilog codes tdb 158 dp gec plessey semiconductor full subtractor circuit using nor gates full adder circuit using nor gates mc2870 VHDL program 4-bit adder 8 bit subtractor | |
GP144Contextual Info: GEC P L E S S E Y Is e m i c o n d u c t o r s MARCH 1992 ! 2462 - 3.1 CLA70000 SERIES HIGH DENSITY CMOS GATE ARRAYS S u persedes Jan uary 1992 edition R ecent advances in CMOS processing technology and im p ro vem e nts in design a rch ite ctu re have led to the |
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CLA70000 GP144 | |
full subtractor circuit nand gates
Abstract: 8 bit carry select adder verilog codes PLESSEY CLA low power and area efficient carry select adder v 32 bit barrel shifter vhdl advantages of master slave jk flip flop half adder 74 full subtractor circuit using nand gate 0-99 counter by using 4 dual jk flip flop 3 bit carry select adder verilog codes
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CLA70000 full subtractor circuit nand gates 8 bit carry select adder verilog codes PLESSEY CLA low power and area efficient carry select adder v 32 bit barrel shifter vhdl advantages of master slave jk flip flop half adder 74 full subtractor circuit using nand gate 0-99 counter by using 4 dual jk flip flop 3 bit carry select adder verilog codes | |
low power and area efficient carry select adder v
Abstract: IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER 16 bit carry select adder 32 bit carry select adder 8 bit carry select adder full subtractor implementation using NOR gate 32 bit ripple carry adder carry select adder full subtractor circuit using nor gates BCD adder use rom
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MVA60000 MVA60000 DS5499 CLA60000 low power and area efficient carry select adder v IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER 16 bit carry select adder 32 bit carry select adder 8 bit carry select adder full subtractor implementation using NOR gate 32 bit ripple carry adder carry select adder full subtractor circuit using nor gates BCD adder use rom | |
full subtractor circuit using decoder and nand ga
Abstract: PLESSEY CLA LC28 full adder 2 bit ic GP144
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CLA70000 full subtractor circuit using decoder and nand ga PLESSEY CLA LC28 full adder 2 bit ic GP144 | |
10B5
Abstract: 93CS46
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PCI9060/68040 PCI9060 32-bit PCI9060, 100ns 200ns 300ns 10B5 93CS46 | |
68040* part numbering
Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
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PCI9060/68040 PCI9060 32-bit PCI9060, 100ns 200ns 300ns 68040* part numbering 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5 | |
Contextual Info: MITSUBISHI LSIs M6MGB/T08S2ATP 8388608-BIT 1 M x 8-BIT/512k x 16-BIT CMOS 3.3V-ONLY FLASH MEMORY & 2097152-BIT (256k x 8-BIT) CMOS STATIC RAM MCP (Multi Chip Package) FEATURES DESCRIPTION The MITSUBISHI M6MGB/T08S2ATP is a Multi Chip Package (MCP) that contents 8-Mbit Flash memory and |
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M6MGB/T08S2ATP 8388608-BIT 8-BIT/512k 16-BIT) 2097152-BIT M6MGB/T08S2ATP 82-pin bytes/524288 M5M29GB/T800A) M5M5V208) | |
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