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    XC6SLX150 Price and Stock

    AMD XC6SLX150T-3FGG484C

    IC FPGA 296 I/O 484FBGA
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    DigiKey XC6SLX150T-3FGG484C Tray 151 1
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    Mouser Electronics XC6SLX150T-3FGG484C 66
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    AMD XC6SLX150-2FG484I

    IC FPGA 338 I/O 484FBGA
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    DigiKey XC6SLX150-2FG484I Tray 120 1
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    AMD XC6SLX150-2FGG484I

    IC FPGA 338 I/O 484FBGA
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    DigiKey XC6SLX150-2FGG484I Tray 68 1
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    AMD XC6SLX150T-2FGG484I

    IC FPGA 296 I/O 484FBGA
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    DigiKey XC6SLX150T-2FGG484I Tray 60 1
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    AMD XC6SLX150-2FGG484C

    IC FPGA 338 I/O 484FBGA
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    DigiKey XC6SLX150-2FGG484C Tray 40 1
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    XC6SLX150 Datasheets (102)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC6SLX150-2CSG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX150-2CSG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX150-2FG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-2FG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-2FG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FCBGA Original PDF
    XC6SLX150-2FG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FCBGA Original PDF
    XC6SLX150-2FG900C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 576 I/O 900FBGA Original PDF
    XC6SLX150-2FG900I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 576 I/O 900FBGA Original PDF
    XC6SLX150-2FGG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-2FGG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-2FGG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FBGA Original PDF
    XC6SLX150-2FGG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FBGA Original PDF
    XC6SLX150-2FGG900C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 576 I/O 900FBGA Original PDF
    XC6SLX150-2FGG900I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 576 I/O 900FBGA Original PDF
    XC6SLX150-3CSG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX150-3CSG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX150-3FG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-3FG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484FBGA Original PDF
    XC6SLX150-3FG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FCBGA Original PDF
    XC6SLX150-3FG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 498 I/O 676FCBGA Original PDF

    XC6SLX150 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: VPX Boards VPX-SLX VPX module with User-Configurable Spartan-6 FPGA Front Panel Mezzanine Bus AXM I/O Module 64 I/O or 32 LVDS Dual-Port SRAM 1M x 32 XC6SLX150 Dual Port SRAM 1M x 32 97 I/O PCIe Bus 4 lanes Flash Memory 16MB XC5VLX30T VPX 3U card with PCIe interface ◆ Logic-optimized Spartan-6 FPGA ◆ Air and conduction-cooled models


    Original     		PDF XC6SLX150 XC5VLX30T 32-BIT 125MHZ 64-BIT LX30T

    xc3s500e fg320

    Abstract: xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 LVCMOS33 CPG196
    Text: XI LI NX S PARTAN -6 FAM I LY FPGAS Spartan-6 LX FPGAs Spartan-6 LXT FPGAs Optimized for Lowest-Cost Logic, DSP, and Memory 1.2 Volt, 1.0 Volt Part Number XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T


    Original     		PDF XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T xc3s500e fg320 xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 LVCMOS33 CPG196

    Untitled

    Abstract: No abstract text available
    Text: Spartan-6 FPGA Clocking Resources User Guide UG382 v1.8 June 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL


    Original     		PDF UG382

    DSP48A1

    Abstract: DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code
    Text: Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 v1.1 August 13, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF DSP48A1 UG389 DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code

    Untitled

    Abstract: No abstract text available
    Text: 89 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Product Specification DS162 v3.0 October 17, 2011 Spartan-6 FPGA Electrical Characteristics Spartan -6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and


    Original     		PDF DS162

    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0

    xc6slx150t

    Abstract: STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2
    Text: LogiCORE IP Fast Fourier Transform v8.0 DS808 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the


    Original     		PDF DS808 xc6slx150t STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2

    winbond* W25Q

    Abstract: UG380 SPARTAN 6 Configuration UG628 SPARTAN 6 spi numonyx spartan 6 LX150 Spartan6 XC6SLX9 winbond w25q W25Q spi flash programmer schematic
    Text: Spartan-6 FPGA Configuration User Guide [optional] UG380 v1.0 June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG380 winbond* W25Q UG380 SPARTAN 6 Configuration UG628 SPARTAN 6 spi numonyx spartan 6 LX150 Spartan6 XC6SLX9 winbond w25q W25Q spi flash programmer schematic

    jesd79f

    Abstract: UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45
    Text: Spartan-6 FPGA Memory Controller User Guide UG388 v2.3 August 9, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG388 com/pdf/technotes/ddr2/TN4708 com/pdf/technotes/ddr2/TN4720 TMS320C6454/5 jesd79f UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45

    XC4VLX15-FF668

    Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
    Text: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		PDF DS317 XC4VLX15-FF668 axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan

    XC7K325TFFG900

    Abstract: XC6SLX45-CSG324 XC3SD3400AFG676 XC7K325T-ffg900 spartan ucf file 6 XC6SLX16-FTG256 XC6SLX25-CSG324-2C XC6SLX16-CSG324 XC6SLX45-FGG484 XC7K355T-FFG901
    Text: LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI DS206 October 19, 2011 Product Specification v3.167 & v4.15 Features LogiCORE IP Facts Table • Fully compatible 32-bit, 66/33 MHz Initiator/Target core for PCI • Customizable, programmable, single-chip solution


    Original     		PDF 32-Bit DS206 32-bit, XC7K325TFFG900 XC6SLX45-CSG324 XC3SD3400AFG676 XC7K325T-ffg900 spartan ucf file 6 XC6SLX16-FTG256 XC6SLX25-CSG324-2C XC6SLX16-CSG324 XC6SLX45-FGG484 XC7K355T-FFG901

    XC6SLX150T-FGG676

    Abstract: xc6slx150t-fgg676-3 XC6SLX150T_FGG676 usb 2.0 implementation using verilog verilog code for uart apb video pattern generator "displayport receiver" xc6slx150t displayport 1.2 SPARTAN-6 GTP
    Text: Application Note: Spartan-6 FPGAs Implementing a DisplayPort Source Policy Maker Using a MicroBlaze Embedded Processor XAPP493 v1.0 July 21, 2010 Summary Author: Tom Strader and Matt Ouellette This application note describes the implementation of a DisplayPort Source Policy Maker


    Original     		PDF XAPP493 TB-6S-LX150-IMG) XC6SLX150T-FGG676-3 XC6SLX150T-FGG676 xc6slx150t-fgg676-3 XC6SLX150T_FGG676 usb 2.0 implementation using verilog verilog code for uart apb video pattern generator "displayport receiver" xc6slx150t displayport 1.2 SPARTAN-6 GTP

    XC6SLX45

    Abstract: XC6SLX150 Xilinx Spartan-6 LX9 XC6SLX75 xc6slx150t XC6SLX25CSG324 XC6SLX4 xc6slx16 XC6SLX4 2 CSG225 I XC6SLX25-CSG324
    Text: 80 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DS162 v2.1 May 20, 2011 Preliminary Product Specification Spartan-6 FPGA Electrical Characteristics Spartan -6 LX FPGAs are available in -3, -3N, -2, and -1L speed grades, with -3 having the highest performance.


    Original     		PDF DS162 XC6SLX45 XC6SLX150 Xilinx Spartan-6 LX9 XC6SLX75 xc6slx150t XC6SLX25CSG324 XC6SLX4 xc6slx16 XC6SLX4 2 CSG225 I XC6SLX25-CSG324

    xc6slx16

    Abstract: XC6SLX45 XC6SLX25 XC6SLX150 XC6SLX9 XC6SLX16 Spartan-6 LX45 efuse XC6SLX150T SPARTAN 6 DS162 CSG324
    Text: 69 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DS162 v1.3 February 22, 2010 Advance Product Specification Spartan-6 FPGA Electrical Characteristics Spartan -6 LX FPGAs are available in -3, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT


    Original     		PDF DS162 xc6slx16 XC6SLX45 XC6SLX25 XC6SLX150 XC6SLX9 XC6SLX16 Spartan-6 LX45 efuse XC6SLX150T SPARTAN 6 DS162 CSG324

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP XPS Universal Serial Bus 2.0 Device v7.01a DS639 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLB) v4.6 enables Universal Serial Bus (USB) connectivity to a user design with a


    Original     		PDF DS639 PLBv46 32-bit

    SPARTAN 6 xc6slx45 pin configuration

    Abstract: XC6SLX45 spartan 6 partial configuration XC6SLX16 Spartan-6 FPGA XC6SLX9 iodelay DSP48A1 XC6SLX100 XC6SLX25
    Text: 10 Spartan-6 Family Overview DS160 v1.3 November 5, 2009 Advance Product Specification General Description The Spartan -6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous


    Original     		PDF DS160 UG382) UG393) UG386) SPARTAN 6 xc6slx45 pin configuration XC6SLX45 spartan 6 partial configuration XC6SLX16 Spartan-6 FPGA XC6SLX9 iodelay DSP48A1 XC6SLX100 XC6SLX25

    UG380

    Abstract: Spartan-6 PCB design guide XC6SLX45T XC6SLX150 XC6SLX25 lx25t XC6SLX100 XC6SLX45 spartan6 block ram iodelay
    Text: 11 Spartan-6 Family Overview DS160 v1.7 March 21, 2011 Preliminary Product Specification General Description The Spartan -6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous


    Original     		PDF DS160 UG383) UG384) UG386) DSP48A1 UG389) UG380 Spartan-6 PCB design guide XC6SLX45T XC6SLX150 XC6SLX25 lx25t XC6SLX100 XC6SLX45 spartan6 block ram iodelay

    CSG324

    Abstract: transistor bl p89 bl p76 transistor transistor bl p85 XC6SLX150T spartan 6 LX150t bl p78 transistor CPG196 CSG484 xc6slx75csg484
    Text: Spartan-6 FPGA Packaging and Pinouts Product Specification UG385 v1.2 February 22, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG385 CSG324 transistor bl p89 bl p76 transistor transistor bl p85 XC6SLX150T spartan 6 LX150t bl p78 transistor CPG196 CSG484 xc6slx75csg484

    XC7Z020CLG400

    Abstract: XC7Z020CLG484 XC7K160Tffg676 XC7Z045FFG900 XC7A200T-FBG484 XC7Z010-CLG400
    Text: LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI DS205 October 16, 2012 Product Specification v3.167 & v4.18 Features LogiCORE IP Facts • Fully compatible 64-bit, 66/33 MHz LogiCORE IP Initiator/Target core for PCI™ • Customizable, programmable, single-chip solution


    Original     		PDF 64-Bit DS205 64-bit, XC7Z020CLG400 XC7Z020CLG484 XC7K160Tffg676 XC7Z045FFG900 XC7A200T-FBG484 XC7Z010-CLG400

    spartan 6 LX150

    Abstract: SPARTAN 6 UG385 CSG484 CSG225 CSG324 SPARTAN-6 transistor bl p89 spartan 6 LX150t transistor bl p44 Tr u28 212
    Text: Spartan-6 FPGA Packaging and Pinouts Product Specification UG385 v1.3 October 12, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG385 spartan 6 LX150 SPARTAN 6 UG385 CSG484 CSG225 CSG324 SPARTAN-6 transistor bl p89 spartan 6 LX150t transistor bl p44 Tr u28 212

    Untitled

    Abstract: No abstract text available
    Text: SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG751 v1.1 September 15, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF SP623 UG751 UG381, UG388, DS080, UG386, DS606, DS614, HW-CLK-101-SCLK2 SP623

    XC6SL

    Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18
    Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18

    XC6SLX

    Abstract: 2ffg1157 xps usb2 XC6SLX150
    Text: LogiCORE IP AXI Universal Serial Bus 2.0 Device v3.00a DS785 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This


    Original     		PDF DS785 ZynqTM-7000, XC6SLX 2ffg1157 xps usb2 XC6SLX150

    xc7a100tcsg324

    Abstract: XC7A200T-FBG484 XC6SLX16CSG324 Xilinx ISE Design Suite 14.2 XC6SLX45-FGG484 XC6SLX100-FGG676 XC6SLX16-CSG324 XC6SLX45-CSG324 XC6SLX9CSG324 XC6SLX45-CSG484
    Text: LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI DS205 July 25, 2012 Product Specification v3.167 & v4.17 Features LogiCORE IP Facts • Fully compatible 64-bit, 66/33 MHz LogiCORE IP Initiator/Target core for PCI™ • Customizable, programmable, single-chip solution


    Original     		PDF 64-Bit DS205 64-bit, xc7a100tcsg324 XC7A200T-FBG484 XC6SLX16CSG324 Xilinx ISE Design Suite 14.2 XC6SLX45-FGG484 XC6SLX100-FGG676 XC6SLX16-CSG324 XC6SLX45-CSG324 XC6SLX9CSG324 XC6SLX45-CSG484