ULTRA37384 Search Results

NCL025

Abstract: tms 0119 Ol73 CY37384P208-66NC 256-pin Plastic BGA 17 x 17 T-33-I u175
Contextual Info: J ^ m n rn n : if : Y PRELIMINARY H Ultra37384 - UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tc o = 6 ns • 384 m a cro c ells in 24 logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

Contextual Info: ,!!!!!!ifSmfím ^ . „ n « Ultra37384V PRELIMINARY UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — ts = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 8 ns • • • • •

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Abstract: DO96
Contextual Info: . „ n « PRELIMINARY Ultra37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

FLASH370I

Abstract: Ultra37032 FLASH370 UltraISRPCCABLE
Contextual Info: fax id: 6451 An Introduction to In-System Reprogramming ISR with the Ultra37000™ Introduction This application note provides an introduction to the Ultra37000™ family of In-System Reprogrammable (ISR™) CPLDs. The Ultra37000 ISR CPLD family upgrades the

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

O16I

Abstract: 7256P 99L0
Contextual Info: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

NCL025

Contextual Info: •■■■■■■\fct>cw.-. s a s iâ s ^ 5^” .w s & v PRELIMINARY _ . "T U ltra 3 7 5 1 2 UltraLogic 512-Macrocell ISR™ CPLD Features • • • • • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

Contextual Info: Si CYPRESS PRELIMINARY Ultra37512 UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • 512 macrocells in 32 logic blocks • In-System Reprogram mable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: fax id: 6141 1CP LD Fa mily Ultra37000 ISR™ CPLD Family PRELIMINARY UltraLogic™ High-Performance CPLDs • Warp2 —Low-cost IEEE 1076/1164-compliant VHDL system —Available on PC, Sun, and HP platforms for $99 —Supports all Cypress Programmable Products

Contextual Info: fax id: 6141 Ultra37000 ISR™ _ C P L D F a m i l y UltraLogic™ High-Performance CPLDs • W a rp 2 Featu res — L o w - c o s t I EE E 1 0 7 6 / 1 1 6 4 - c o m p l i a n t V H D L s y s t e m I n-System R e p r o g r a m m a b l e I S R ™ C M O S C P L D s

FLASH370

Abstract: UltraISRPCCABLE cypress ultra37000 jtag bga 84
Contextual Info: An Introduction to In-System Reprogramming ISR with the Ultra37000™ Introduction This application note provides an introduction to the Ultra37000™ family of In-System Reprogrammable™ (ISR™) CPLDs. The Ultra37000 ISR CPLD family upgrades the FLASH370i™ CPLD family of devices and provides higher

ULTRA37000

Contextual Info: fax id: 6141 y Ultra37000 ISR™ CPLD Family PRELIMINARY UltraLogic™ High-Performance CPLDs • Warp2 —Low-cost IEEE 1076/1164-compliant VHDL system —Available on PC, Sun, and HP platforms for $99 —Supports all Cypress Programmable Products • Warp2Sim™ adds:

FLASH370

Contextual Info: fax id: 6451 Back An Introduction to In-System Reprogramming ISR with the Ultra37000™ Introduction This application note provides an introduction to the Ultra37000™ family of In-System Reprogrammable (ISR™) CPLDs. The Ultra37000 ISR CPLD family upgrades the

Contextual Info: y Ultra37000 ISR™ CPLD Family PRELIMINARY UltraLogic™ High-Performance CPLDs • Warp2 —Low-cost IEEE 1076/1164-compliant VHDL system —Available on PC, Sun, and HP platforms for $99 —Supports all Cypress Programmable Products • Warp2Sim™ adds:

Contextual Info: PRESS RELEASE CYPRESS'S NEW CPLD FAMILY IS SIMPLY THE WORLD'S FASTEST Devices from 32 to 512 Macrocells Offer Worst-Case Delays as Low as 5 ns, Cypress ISR SAN JOSE, Calif., May 11, 1998 - Cypress Semiconductor NYSE:CY today unveiled a new family of Complex Programmable Logic Devices (CPLDs) that offers unparalleled speed,