ULTRA37128 Search Results

Contextual Info: fax id: 6146 s? CYPRESS Ultra37128 PRELIMINARY UltraLogic 128-Macrocell ISR™ CPLD • High speed Features — f MAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — t PD = 6.5 ns — ts = 3.5 ns — JTAG compliant on board programming

Ultra37128

Abstract: 37128VP100
Contextual Info: fax id: 6147 PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 125 MHz • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — tPD = 10 ns

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: . „ n « PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: fax id: 6146 s? CYPRESS Ultra37128 PRELIMINARY UltraLogic 128-Macrocell ISR™ CPLD • High speed Features — f MAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — t PD = 6.5 ns — ts = 3.5 ns — JTAG compliant on board programming

Contextual Info: . „ n « Ultra37128V PRELIMINARY UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

CY37128P160-125AC

Abstract: cpld internal CY3600 CY37128P100-167AC Ultra37128 CY37128P84-125JI
Contextual Info: fax id: 6146 : : M : : IP *: ; M : : Ultra37128 .PRELIMINARY W CYPRESS UltraLogic 128-Macrocell ISR™ CPLD Features High speed f|\/lAX = 167 M Hz • 128 m a cro c ells in eig h t logic blocks — t PD = 6.5 ns • In-S ystem R e p ro g ra m m ab le IS R ™

CY3600

Abstract: tI11J CY37128P84-125JI
Contextual Info: fax id: 6146 ÆÊ PRELIMINARY F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö Ultra37128 U ltraLogic 128-Macrocell IS R ™ CPLD H ig h s p e e d Features — • 128 m a c ro c e lls in e ig h t lo g ic b lo c k s f MAX = 167 M H z — t PD = 6.5 ns

l11J

Abstract: CY3600 cpld internal
Contextual Info: fax id: 6147 ÆÊ F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — f MAX = 125 M Hz • 128 m a cro c ells in eig h t log ic blocks — t PD = 10 ns • 3 .3 V In-S ystem R e p ro g ra m m ab le IS R ™

lem la 100-P

Abstract: E1101
Contextual Info: Ultra37128 P R E U M IN A m UltraLogic 128-Macrocell ISR™ CPLD Features — t co = 4.5 ns P ro d uct-term clo ckin g • 128 m a cro c ells in eig h t logic blocks IEEE1149.1 JTAG b o u n d a ry scan • In-S ystem R e p ro g ra m m ab le IS R ™

CY3600

Abstract: 37128VP100
Contextual Info: fax id: 6147 1Ult ra371 28 V PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 125 MHz • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG compliant on board programming

CY37128P84-125JI

Abstract: Ultra37000TM CY3600 37128P100
Contextual Info: fax id: 6146 1Ult ra371 28 PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG compliant on board programming — tPD = 6.5 ns

Contextual Info: fax id: 6147 W CYPRESS PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — f MAX = 1 2 5 M H z • 128 macrocells in eight logic blocks • 3.3V In-System Reprogram mable ISR™ — t PD = 10 ns — ts = 5.5 ns

Contextual Info: fax id: 6147 W CYPRESS PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — f MAX = 1 2 5 M H z • 128 macrocells in eight logic blocks • 3.3V In-System Reprogram mable ISR™ — t PD = 10 ns — ts = 5.5 ns

FLASH370I

Abstract: Ultra37032 FLASH370 UltraISRPCCABLE
Contextual Info: fax id: 6451 An Introduction to In-System Reprogramming ISR with the Ultra37000™ Introduction This application note provides an introduction to the Ultra37000™ family of In-System Reprogrammable (ISR™) CPLDs. The Ultra37000 ISR CPLD family upgrades the

Contextual Info: fax id: 6150 PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Features • • • • • • • • • • • 192 macrocells in twelve logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

tlp 453

Contextual Info: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant

Contextual Info: Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE1149.1 JTAG boundary scan

CY37256VP160-100AC

Abstract: h jtag
Contextual Info: fax id: 6149 PRELIMINARY Ultra37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR — tCO = 6.5 ns Product-term clocking IEEE1149.1 JTAG boundary scan

Contextual Info: . „ n « PRELIMINARY Ultra37064 UltraLogic 64-Macrocell ISR™ CPLD — ts = 3.5 ns Features — tco = 4.5 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ ISR™ • • • • • • • — JTAG-compliant on-board programming

Contextual Info: fax id: 6150 CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

Contextual Info: fax id: 6146 . a É | % m n r n n PRELIMINARY U ltra 3 7 1 2 8 UltraLogic 128-Macrocell ISR™ CPLD • High speed Features ^MAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — t PD = 6.5 ns — ts = 3.5 ns

Contextual Info: fax id: 6149 CYPRESS UltraLogic 3.3V 256-Macrocell ISR™ CPLD PRELIMINARY Ultra37256V — t PD = 12 ns Features — ts = 6 ns • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — tco = 7 ns — 3.3V ISR — 5V tolerant • 3.3V In-System Reprogram mable ISR™

Contextual Info: CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability