T74LS114A Search Results

Contextual Info: S G S-THOMSON 42E D 0033340 SCS-THO M SO Ü 3 ISûTH T -y é - O T - o i T7 4 L S 114A [R{tlD i ê [l[LIl(g?^(s)[î!!lD(gi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N The T74LS114A offer common clock and common clear Inputs and Individual J, K, and set inputs. The­

Contextual Info: £ ÿ j S C S -T H O M S O N L ìO T q * ì T74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N The T74LS114A offer common clock and common clear inputs and individual J, K, and set inputs. The­ se monolithic dual flip-flops are designed so that

WCL 209

Abstract: ltzt
Contextual Info: as DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are de­ signed so that when the clock goes HIGH, the in­ puts are enabled and data will be accepted. The

T74LS244

Abstract: T74LS5 t74LS161a sgs T74LS293 T74LS02
Contextual Info: ALPHANUMERICAL INDEX I Type Number T74LS00 T74LS01 T74LS02 T74LS03 T74LS04 T74LS05 T74LS08 T74LS09 T74LS10 T74LS11 T74LS12 T74LS13 T74LS14 T74LS15 T74LS20 T74LS21 T74LS22 T74LS26 T74LS27 T74LS28 T74LS30 T74LS32 T74LS33 T74LS37 T74LS38 T74LS40 T74LS42 T74LS51

t114a

Abstract: 1t4a T54LS/T74LS114/114A
Contextual Info: S G K ? C m Î i S-THOnSON $ 1 ÎM 07E M D | 7^5^53? 0 UJi hü 31 4 | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i l Ì T 7 4 L S t1 4 |M 67C 1 6 1 6 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and