SCAS838 Search Results

74SSTUB32864AZKER

Abstract: Q11A Q13A
Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

SB865A

Abstract: SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866
Contextual Info: Application Report SCAA101 – March 2009 DDR2 Memory Interface Clocks and Registers – Overview Christian Schmoeller . CDC - Clock Distribution Circuits ABSTRACT This application report gives an overview of the existing JEDEC DDR2 Register and